SANTA CLARA, Calif. – Nov. 8, 2023 – Ayar Labs, a company developing silicon photonics for chip-to-chip connectivity, will showcase its in-package optical I/O solution integrated with Intel’s Agilex Field-Programmable Gate Array (FPGA) technology. In demonstrating 5x current industry bandwidth at 5x lower power and 20x lower latency, the optical FPGA – packaged in a common […]
Optical I/O Takes Center Stage at SC23
November 7, 2023 by Leave a Comment
[SPONSORED GUEST ARTICLE] Integration of optical I/O with an FPGA is the tip of the iceberg of a new vision to enable new HPC/AI architectural advances through ubiquitous optical interconnects for every piece of compute silicon. If you are attending SC23 November 12-17, be sure to visit Ayar Labs in booth #228 for an exclusive look at the future….
Ayar Labs Adds $25M to its Series C
May 25, 2023 by
SANTA CLARA, Calif. – May 24, 2023 – Ayar Labs, a developer of silicon photonics for chip-to-chip connectivity, today announced it has raised an additional $25 million in Series C1 funding, bringing its total Series C raise to $155 million. The oversubscribed up round was led by new investor Capital TEN. VentureTech Alliance also entered the […]
Silicon Photonics and the Hunt for an HPC Bandwidth Bottleneck Breakthrough
December 19, 2022 by
[SPONSORED CONTENT] “FLOPS are cheap, moving data is expensive.” In HPC circles this sentiment is heard often. There’s a growing sense that classical HPC systems and the advanced chips that power them are pushing up against their practical limits, that some foundational new technology is needed to build more balanced systems to achieve the next […]
Ayar Labs Wins $15M Optical I/O Contract from DoD
November 10, 2022 by
SANTA CLARA, Calif. – Nov. 10, 2022 – Ayar Labs, a developer of chip-to-chip optical connectivity, was awarded a $15 million multi-year prototype Other Transaction Agreement (OTA) in support of Project KANAGAWA (the Co-Packaged Analog-Drive High-Bandwidth Optical Input/Output Project). The OTA, a non-traditional government contracting method for fast tracking research and innovation, was issued by Naval Surface […]
Lockheed Martin, Ayar Labs Partner on Microchip Connectivity for Sensory Systems
October 17, 2022 by
BETHESDA, Md. and SANTA CLARA, Calif. – Lockheed Martin, (NYSE: LMT) and Ayar Labs, a leader in chip-to-chip optical connectivity, today announced a strategic collaboration to develop future sensory platforms that leverage Ayar Labs’ advanced optical I/O microchips that use light to transfer data faster, at a lower latency, and at a fraction of the […]
Optical I/O Company Ayar Labs Raises $130M in Series C Funding
April 26, 2022 by
SANTA CLARA, Calif. – April 26, 2022 – Ayar Labs, a chip-to-chip optical connectivity company, today announced that the company has secured $130 million in additional financing led by Boardman Bay Capital Management to drive the commercialization of its breakthrough optical I/O solution. Hewlett Packard Enterprise (HPE) and NVIDIA entered this investment round, joining existing […]
HPE and Ayar Labs Partner to Bring Optical I/O to Slingshot Fabric for HPC and AI
February 24, 2022 by
HPC systems leader Hewlett Packard Enterprise and startup Ayar Labs, maker of chip-to-chip optical I/O connectivity, today announced a strategic collaboration to integrate silicon photonics within HPE’s high performance Slingshot fabric. Longer term, HPE envisions future generations of HPC systems interconnects significantly enhanced by optical I/O, which is a silicon photonics-based technology that uses light instead of electricity to transmit data. The technology addresses both the need for higher data rates and improved energy efficiency (see “Composable HPC-AI at Scale: The Emergence of Optical I/O Chiplets”).
Composable HPC-AI at Scale: The Emergence of Optical I/O Chiplets
December 13, 2021 by
The allure of “technology resource disaggregation” – a.k.a., composable computing – doesn’t get old. It’s an ingenious yet common-sense strategy for addressing our increasingly heterogeneous HPC-AI world where no single system can cost-effectively satisfy the range of workloads needed to be kept in play, each workload having its own unique combination of system requirements that would otherwise produce, in a single system, “marooned” resources that sap budgets. Put another way, with a composable HPC infrastructure there are pools of compute, memory, and storage resources enabling the dynamic assembly of customized nodes on a per-workload basis, offering configuration of “Goldilocks” solutions.
Overcoming Bandwidth and Capacity Bottlenecks in the Exascale Era
October 21, 2021 by
[SPONSORED POST] Join us for the Advanced Memory Architectures to Overcome Bandwidth Bottlenecks for the Exascale Era of Computing webinar on November 10 at 9:00 am PT. During this webinar, leading industry experts will discuss the future of advanced memory architectures, new optical I/O solutions using silicon photonics, and the technologies and environments needed to make next-generation performance a reality.
