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@HPCpodcast: CXL News, the CHIPS Act, Chips and Nm and Chip ‘Sprawl’

We’ve heard so much about the CXL interconnect – including the recent announcement of CXL v3.0 – and components that are CXL-ready, that it may come as a surprise that CXL v1.1 “hosts” are only just now shipping. It’s a technology that could play a central role in the ever-more heterogenous, more memory-intensive systems of the future. And now, after several years of experimentation and various interconnect consortia, CXL is emerging as the standard for advanced functionality for fabric technologies. Along with CXL we also discuss some of the details of the CHIPS and Science Act….

The Evolution of HPC Storage: More Choices Yields More Decisions

[SPONSORED CONTENT] The past few years have brought many changes into the HPC storage world, both with technology like non-volatile memory express (NVMe) or persistent memory, and the growth of software defined storage solutions. Gone are the days when IBM Spectrum Scale (secretly, we know we all still call it GPFS) or Lustre were the only real choices in the market. In retrospect, the choice was easy: you picked one of the two and away you went.  And nobody ever wondered if they made the right choice.   

Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform

SANTA CLARA, CA, U.S. – November 15, 2021 – Astera Labs, make of connectivity solutions for intelligent systems, today announced its new Leo Memory Accelerator Platform for Compute Express Link (CXL) 1.1/2.0 interconnects to enable disaggregated memory pooling and expansion for processors, workload accelerators, and smart I/O devices. Leo overcomes processor memory bandwidth bottlenecks and […]

CXL Consortium at SC21: 1st Public Demo of Compute Express Link

November 15, 2021 – Beaverton, OR – The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, will showcase growing momentum for CXL technology at Supercomputing (SC21), taking place at America’s Center in St. Louis, Missouri and virtually November 15-18. The CXL specification enables a high-speed, efficient interconnect between the CPU and […]

Samsung Claims First Open-source Software for CXL Memory Platform

Samsung today introduced what it said is the first open-source software solution designed for the Compute Express Link (CXL) memory platform. The company said the Scalable Memory Development Kit (SMDK) builds on Samsung’s May launch of a CXL memory expander, designed to allow memory capacity and bandwidth to scale to levels exceeding server system limits. […]

Tear Down These Walls: How CXL Could Reinvent the Data Center

The move to heterogenous computing will require shifting some … interconnects to a more performant industry standard interface enabling new capabilities like memory tiers, pooled memory, and even the convergence of memory and storage. And to unshackle architectural innovation and choice, we need an open standard with broad industry acceptance. Enter the Compute Express Link (CXL). CXL is an open interface that standardizes a high-performance interconnect for data-centric platforms – it provides the ability to connect CPUs to XPUs, storage, memory and networking, enabling increased degrees of freedom for platform architecture via the ability to build more optimized infrastructures.

Micron Updates Memory and Storage Strategy – Commits to CXL, Ends Development of 3D XPoint

BOISE, Idaho, March 16, 2021 — Micron Technology, Inc. (Nasdaq: MU), today announced updates to the company’s portfolio strategy to focus on memory and storage for the data center. Micron will increase investment in new memory products that leverage the Compute Express Link (CXL), the recently introduced industry standard interface that enables flexible connection between […]

CXL Consortium Releases Compute Express Link 2.0 Spec

The CXL Consortium has announced the release of the Compute Express Link 2.0 specification, which adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory – while preserving industry investments by supporting full backwards compatibility with […]

Gen-Z Consortium’s Activity Lineup at Upcoming Flash Memory Summit, SC20

The Gen-Z Consortium has announced it will participate in the upcoming Flash Memory Summit and SC20 conferences. Along with speaking engagements and panel participation, the interconnect consortium will showcase Gen-Z technology demos from member companies in GenZ’s virtual booths. Flash Memory Summit, Nov. 10-12, will include online presentations along with a virtual exhibit hall featuring […]

Astera Labs lands funding for purpose-built connectivity solutions

Today Astera Labs announced that it has closed its Series B funding with renowned technology investors including Sutter Hill Ventures, Intel Capital, Avigdor Willenz, and Ron Jankov. This investment round, along with a strategic collaboration with TSMC for manufacturing, positions Astera Labs to rapidly scale production of its Aries Smart Retimer, the world’s first Smart Retimer Portfolio for PCI Express (PCIe) 4.0 and 5.0 solutions, and to accelerate development of additional product lines for Compute Express Link (CXL) solutions. “We are very proud of the significant industry traction for our Aries Smart Retimer Portfolio which has been extensively tested with all major CPU, GPU and PCIe 4.0 endpoints,” said Jitendra Mohan, CEO, Astera Labs. “We look forward to accelerating this momentum by partnering with such a distinguished group of technology and manufacturing heavyweights to develop purpose-built connectivity solutions for data-centric systems.”