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Tilera 100 Core x86 Architecture

TGDaily posted a rare interview late last night with a silicon start-up company running under the industry radar.  Tilera has released, via a 40nm process, what they call their TILE line of x86 processors.  Plot thickens, you can get up to 100 cores in a single socket.  The Tile-Gx, as its called, only clocks in at around 1.50Ghz, but it packs a serious core density punch and only utilizes upwards of 55 watts.

The TILE-Gx line, available with 16, 36, 64 and 100 cores, employs Tilera’s unique architecture that scales well beyond the core count of traditional microprocessors,” Tilera spokesperson Bob Doud told TG Daily. “Tilera’s two-dimensional iMesh interconnect eliminates the need for an on-chip bus and its Dynamic Distributed Cache (DDC) system allows each cores’ local cache to be shared coherently across the entire chip.”

Of course, 100 cores is nothing without software.  Linux has become Tilera’s operating system of choice.  More specifically, they’ve chosen Zol Linux, or zero overhead Linux.

Our processors are extremely standard in terms of Linux, which has been successfully ported to dozens of platforms. And once you have Linux running, there a number of tools that offer support for C++ and Java,” explained Doud. “Tilera provides a multicore development environment for its TILE-Gx processors that includes a GCC compiler, standard gdb gprof, Eclipse IDE, multicore debug and multicore profile. In addition, our standard application stack offers a bare metal environment, hypervisor layer, virtualization capabilities, I/O devices drivers and a load balancer.”

Tilera 100 core100 cores is neat, but what else does the TILE-Gx line offer in the way of silicon goodness?

  • Next-generation 64-bit core: New three-issue 64-bit core with full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.
  • Enhanced SIMD instruction extensions: Enhanced signal processing performance with a 4 MAC/cycle multiplier unit delivering up to 600 billion MACs per second, more than 12x the fastest commercial DSP
  • Integrated high-performance DDR3 memory controllers: Two or four 72-bit controllers running up to 2133 MHz speeds with ECC support. Up to 1TB total capacity and supporting memory striping modes for maximum utilization.
  • Hardware acceleration engines: On-chip MiCA (Multistream iMesh Crypto Accelerator) system delivers up to 40Gbps encryption and 20Gbps full duplex compression processing, tightly coupled to the core array for extremely low latency and wire-speed small packet throughput.  A high-performance true random number generator (RNG) and public key accelerator enable up to 50,000 RSA handshakes per second.
  • Packet processing accelerator: mPIPE (multicore Programmable Intelligent Packet Engine) system provides wire-speed packet classification, load balancing and buffer management. This flexible, C-programmable engine delivers 80 Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.

This architecture looks very tasty for certain applications.  Keep an eye on Tilera and those that decide to potentially integrate this technology into their respective platforms.  For more info, read the full overview here.

Comments

  1. As far as I can tell, from their website, this is /not/ x86. If it were, it would be a tremendous selling point, and they don’t mention it at all.

  2. I agree with Alex. If it were x86 I’m sure that Intel would be ahead on this one. I imagine that’s why Linux is it’s operating system of choice. You can recompile linux from source for any architecture but since windows is not open source it’s not an option. (Of course if it IS x86, then any x86 code should work, including windows, and any pre-compiled Linux distribution.

    This article seems to indicate that it is actually competing with x86.
    http://www.tgdaily.com/hardware-features/44417-tilera-challenges-x86-architecture-with-100-core-processor

    Does anyone know where to find which architecture it uses for sure? Link?

  3. Looking more… I think it seems to be an un-named architecture? According to Wikipedia it uses a “MIPS-derived … instruction set”. Which doesn’t say much since a lot of architectures have similarities to a MIPS processor.

    Also, here is another article that seems to indicate that it is NOT x86.

    “But it’s this architecture issue that’s Tilera’s biggest weak point”
    http://gigaom.com/2009/10/25/chip-startup-tilera-dreams-the-impossible-dream/

    Maybe the name of the company “Tilera” will also be the name of this architecture.

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