I’ll spare you the expansion of the acronym, but Raytheon Co. (yes, that Raytheon) is discussing details of a computer architecture that can adopt different forms depending on the application targeted for it (like an FPGA). The chip was “developed for the Department of Defense to address the large data volume of sensor systems.”
There aren’t a lot of details yet, but according to the company:
The company has begun tests on prototypes of the polymorphic MONARCH processors to verify they’ll function as designed and to establish their maximum throughput and power efficiency. MONARCH, containing six microprocessors and a highly interconnected reconfigurable computing array, provides 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
Blogger Cahya Prastyanto has a few more details:
According to Raytheon’s presentation materials, the six processors inside the MONARCH are of RISC scaler architecture and are capable of Altivec-like SIMD operations. The processor contains 96 adders (fixed and float), 96 multipliers, 124 dual port memories, 258 address generators, 12MB on-chip DRAM, 14 DMA engines and 20 DIFL (differential IFL) ports capable of 1.3 GB per second each.
Again, from the company’s web site:
“Typically, a chip is optimally designed either for front-end signal processing or back-end control and data processing,” explained Nick Uros, vice president for the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems. “The MONARCH micro-architecture is unique in its ability to reconfigure itself to optimize processing on the fly. MONARCH provides exceptional compute capacity and highly flexible data bandwidth capability with beyond state-of-the-art power efficiency, and it’s fully programmable.”
“In laboratory testing MONARCH outperformed the Intel quad-core Xeon chip by a factor of 10,” said Michael Vahey, the principal investigator for the company’s MONARCH technology.