AMD announces ISA extensions for HPC

AMD announced today they’re adding new instruction set extensions designed to improve performance in HPC, multimedia, and security apps. AMD logo

The extensions, called SSE5, evolve the Streaming SIMD Extensions introduced originally in 1999. Although AMD is making the specification available starting today to foster a dialogue with developers, they won’t appear in product until AMD’s Bulldozer core is available in 2009. (Really? Bulldozer?)

The Register dug into the spec a little

For one, AMD will follow the RISC crowd with support for 3-Operand Instructions – up from two. So, unlike in the past where you would do A plus B and then have to store the result of the operation in A or B, developers can now store the result in a third location. This should reduce the total number of instructions needed to perform certain tasks and require less effort on the part of developers to keep track of registers.

The support for 3-Operand Instructions allows AMD to roll out a “fused multiply accumulate” instruction as well. This melds multiplication and addition to permit “iterative calculations with one instruction.”

Read the spec for yourself at http://developer.amd.com/sse5.jsp.

Trackbacks

Resource Links: