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Update on the Illinois UPCRC

The EE Times last week ran an article summarizing some of the key milestones hit by researchers at the two-year old Universal Parallel Computing Research Center at U of Illinois (slides for which are online).

Rick Merritt covers the three new silicon efforts being undertaken at the center, as well as several software efforts.

The newest and perhaps most ambitious of the trio, called DeNovo, is an effort to define a new and more disciplined way of using shared memory. It is working in tandem with a separate project to define a deterministic, parallel language initially based on a parallel version of Java and ultimately migrating to a parallel version of C++.

…”Several of us believe today’s shared memory model is fundamentally broken,” said University of Illinois researcher Sarita Adve, working on DeNovo. “We still want a global address space, but we need a more disciplined programming model with more explicit structures and effects,” she said.

The other two silicon efforts are Rigel (a 1,024-core processor) designed for task-parallel jobs and Bulk Architecture

A third chip design, called Bulk Architecture, is testing the concept of so-called atomic transactions. It defines a compilation stage that gathers groups of instructions into clusters and synchronizes when they are executed to create parallelism.

In terms of software, most of the applications that the article highlights sound dismaying mundane (a parallel browser?), but I suspect once I dig into the presentation material I’ll turn up more meaty projects

At least two projects are developing new kinds of object-oriented data structures needed for highly parallel systems. Such data structures are aimed at shielding programmers from the complexity of highly parallel chips such as the memory hierarchies and coherency structures they are likely to require.

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