In this video, Jay Boisseau discusses how Supercomputing has become the third pillar of science over the coarse of the last 30 years. Today TACC announced that it will deploy a new 10 Petaflop system called Stampede, which will be built by TACC in partnership with Dell and Intel to support for four years the nation’s scientists in addressing the most challenging scientific and engineering problems. Stampede is expected to be up and running in January 2013.
Stampede will be one of the most powerful systems in the world and will be uniquely comprehensive in its technological capabilities,” said TACC Director Jay Boisseau. “Many researchers will leverage Stampede not only for massive computational calculations, but for all of their scientific computing, including visualization, data analysis, and data-intensive computing. We expect the Stampede system to be an exemplar for supporting both simulation-based science and data-driven science.”
When deployed in 2013, Stampede will be the most powerful system in the NSF XD environment, currently the most advanced, comprehensive, and robust collection of integrated digital resources and services enabling open science research in the world.
When completed, Stampede will comprise several thousand Dell “Zeus” servers with each server having dual 8-core processors from the forthcoming Intel® Xeon® Processor E5 Family (formerly codenamed “Sandy Bridge-EP”) and each server with 32 gigabytes of memory. This production system will offer almost 2 petaflops of peak performance, which is double the current top system in XD, and the real performance of scientific applications will see an even greater performance boost due to the newer processor and interconnect technologies. The cluster will also include a new innovative capability: Intel® Many Integrated Core (MIC) co-processors codenamed “Knights Corner,” providing an additional 8 petaflops of performance. Intel MIC co-processors are designed to process highly parallel workloads and provide the benefits of using the most popular x86 instruction set.
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