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DARPA Shoots for Power Efficiency Revolution with PERFECT Workshop

 

One of the toughest hurdles on the road to Exascale is processing power efficiency. This week DARPA announced a new initiative called the Power Efficiency Revolution for Embedded Computing Technologies, or PERFECT. The initiative will kick off with a Proposer’s Day Workshop in Arlington, Virginia on February 15.

PERFECT aims to achieve the 75 GFLOPS/w goal by taking novel approaches to processing power efficiency. These approaches include near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively use the resulting concurrency and tolerate the resulting increased rate of soft errors. The program seeks to leverage and incorporate anticipated industry fabrication geometry advances to 7 nanometers. PERFECT does not plan to build hardware, rather it seeks to develop a simulation capability to measure and demonstrate progress. It plans to specifically address embedded systems processing power efficiencies and performance, and is not concerned with developments that focus on exascale processing issues.

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