Today Micron Technology announced plans to adapt its Hybrid Memory Cube (HMC) for petascale supercomputer systems, which could become a dramatic step forward in memory technology. HMC is designed for applications requiring low-energy, high-bandwidth access to memory, an important requirement for supercomputers. Other applications include data packet processing, data packet buffering or storage, and processor acceleration.
Micron and Fujitsu, a global leader in supercomputing, will each exhibit a display board that features HMC devices in Fujitsu’s next-generation supercomputer prototype at the Supercomputing ’13 Conference in Denver, November 19—21.
Our system designers are highly impressed with HMC because it enables new memory system designs that support our increased demand for bandwidth, super-compact form factor, and optimized energy per bit,” said Yuji Oinaga, head of Fujitsu’s Next Generation Technical Computing Unit. “For optimal performance efficiency of the application software, it is essential to improve the B(Bytes)/F(Flops) ratio, and HMC represents the new standard in memory performance for supercomputing.”
An industry breakthrough, HMC uses advanced through-silicon vias (TSVs)—vertical conduits that electrically connect a stack of individual chips—to combine high-performance logic with Micron’s state-of-the-art DRAM. Micron’s HMC delivers an unprecedented 160 GB/s of memory bandwidth while using up to 70 percent less energy per bit than existing technologies, which dramatically lowers customers’ total cost of ownership (TCO).
HMC has been recognized by industry leaders and influencers as the long-awaited answer to the growing gap between the performance improvement rate of DRAM and processor data consumption rates. Micron’s HMC was recently named Memory Product of the Year by leading electronics publications, EDN and EE Times.
Micron expects volume production of both the 2GB and 4GB HMC devices later in 2014.
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