Report available from workshop on Exascale Interconnection Networks

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Jeff Vetter sent a note over the email transom Friday (sorry I didn’t get to it sooner, Jeff) about a workshop that Oak Ridge and Sandia have just wrapped up on a key technology for exascale-class machines: the network. From his email

The workshop’s goal was to prioritize the challenges in HPC interconnection networks, looking toward deployment of Exascale supercomputers within the next decade; it provided a comprehensive view of the problem by bringing together experts in the fields of interconnects, system software, applications, and device technologies. The seventy-six attendees were from a wide variety of institutions, spanning academia, industry and government, including representatives from the Department of Energy (DOE) Office of Science, National Nuclear Security Administration, National Science Foundation, Defense Advanced Research Projects Agency, and the Department of Defense. Two days of discussion focused on ranking these challenges in four areas: network topologies and routing; processor network interfaces; device technologies; and, performance prediction and simulation. The group’s findings include a prediction of a move toward photonics and chip stacking to help mitigate system energy requirements, and a challenge of improving the performance of the processor network interface by integrating on-chip and off-chip networks. The event was sponsored by the DOE Institute for Advanced Architectures and Algorithms ( – a joint institute between Oak Ridge National Laboratory and Sandia National Laboratories. The final workshop report with findings and recommendations is now available at