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ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification


In this video, Jeffrey Fong presents: ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification.

Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in addressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper presents a scalable parallel architecture, named ParaSplit, for high-performance packet classification. We propose a rule set partitioning algorithm based on range-point conversion to reduce the overall memory requirement. We further optimize the partitioning by applying the Simulated Annealing technique. We implement the architecture on a Field Programmable Gate Array (FPGA) to achieve high throughput by exploiting the abundant parallelism in the hardware.”

Recorded at the Hot Interconnects 2012 conference in Santa Clara. Download the slides (PDF).

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