AMD today announced the AMD Versal Premium VP1902 adaptive system-on-chip (SoC), which the company said is the largest1 adaptive SoC. The processor is an emulation-class, chiplet-based device for streamlining the verification of semiconductor designs. Offering 2X2 the capacity over the prior generation, AMD said designers can innovate and validate application-specific integrated circuits (ASICs) and SoC designs to help bring technologies to market faster.
AMD said the VP1902 has 18.5M logic cells for 2X2 higher programmable logic density and 2X4 aggregate I/O bandwidth compared to the previous generation Virtex UltraScale+ VU19P FPGA.
“Delivering foundational compute technology to enable our customers is a top priority. In emulation and prototyping, that means delivering the highest capacity and performance possible,” said Kirk Saban, corporate vice president, Product, Software, & Solutions Marketing, Adaptive and Embedded Computing Group, AMD. “Chip designers can confidently emulate and prototype next-generation products using our VP1902 adaptive SoC, accelerating tomorrow’s innovations in AI, autonomous vehicles, Industry 5.0 and other emerging technologies.”
AI workloads are driving increased complexity in chipmaking, requiring next-generation solutions to develop the chips of tomorrow, AMD said. FPGA-based emulation and prototyping provides the highest level of performance, allowing faster silicon verification and enabling developers to shift left in the design cycle and begin software development before silicon tape-out. AMD, through Xilinx, brings over 17 years of experience and six generations of emulation devices, which have nearly doubled in capacity each generation3, according to the company.
As complexity grows in ASIC and SoC designs, especially with the rapid advancement of AI and ML-based chips, extensive verification of both silicon and software before tape-out is a must. Debug is essential for pre-silicon verification and concurrent software development. Finding and addressing bugs before tape-out keeps programs on schedule and budget. The VP1902 adaptive SoC leverages the Versal architecture, including the programmable network-on-chip, to provide up to 8X5 faster debugging compared to the prior generation VU19P FPGA, AMD said
The AMD Vivado ML design suite provides customers with a comprehensive development platform to quickly design, debug and validate next-generation applications and technologies and accelerate time to market. New features that support more efficient development on the VP1902 adaptive SoC include automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and enhanced back-end compilation, which enables end users to iterate IC designs faster.
AMD collaborates closely with the EDA community to help customers turn their innovations and technology vision into reality. Working closely with the top EDA vendors, including Cadence, Siemens and Synopsys helps designers access an ecosystem of fully-featured and scalable solutions.
The AMD Versal Premium VP1902 adaptive SoC will begin sampling in Q3 to early access customers with production expected in the first half of 2024.
1 Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus the Intel Stratix 10 GX 10M FPGA. (VER-002)
2 Based on AMD internal analysis in May 2023, comparing the number of system logic cells of the Versal Premium VP1902 device versus the Virtex UltraScale+ VU19P device. (VER-001)
3 Based on AMD internal analysis in June 2023, comparing the number of system logic cells of the Versal Premium VP1902 device versus the Virtex 5 LX330T device and calculating an average across six generations. (VER-010)
4 Based on AMD Labs testing using an A6865 package to simulate the XPIO data rate performance of an AMD Versal Premium VP1902 device versus the published data rate of an AMD Virtex UltraScale+ VU19P FPGA. Actual results will vary. (VER-003)
5 Based on AMD internal analysis in May 2023, comparing the readback/writeback performance of an AMD Versal adaptive SoC CFI interface versus an AMD Virtex UltraScale+ FPGA ICAP interface. Actual performance will vary. (VER-004)
