With the introduction of the A6 Kaveri chip last week, AMD is delivering on its vision of Heterogeneous System Architecture (HSA). While not necessarily designed for HPC, the new devices are intriguing as a sneak peek as to what the future might hold.
In a new white paper, AMD is redefining the idea of a Compute Core: Any core capable of running at least one process in its own context and virtual memory space, independently from other cores.
Over the past 40 years the mechanisms used to advance microprocessor performance and capabilities have evolved greatly, from executing a single instruction at a time on a single processor to executing many parallel instructions on many symmetric cores. Most recently a microprocessor capability might have been determined by its operating frequency and/or the number of CPU cores. With the continued integration of different processor cores, accelerators, and other processing elements, the traditional labeling has become less representative of a processor’s capability. Now with the introduction of single chip heterogeneous computing, a new measure of identification and comparison is required. To this end, the best general measure for the next generation of processors is to count all execution units that are capable of performing in the same compute capacity as the traditional central processing unit (CPU). In this paper, these will be referred to as “Compute Cores” (CC).
In this video from SC13, Vinod Tipparaju presents an Heterogeneous System Architecture Overview.