Over at Wired Magazine, Robert McMillan writes that DARPA is funding a new program called UPSIDE that will investigate analog computing as a means of achieving better power efficiency. The idea is to have chipmakers build analog processors that can do probabilistic math without forcing transistors into an absolute one-or-zero state, a technique that burns […]
Archives for August 2012
Video: Power-Efficient, High-Bandwidth Optical Interconnects for HPC
August 27, 2012 by
httpv://www.youtube.com/watch?v=BQM5KYxtVPk In this video, Fuad Doany from IBM T. J. Watson presents: Power-Efficient, High-Bandwidth Optical Interconnects for High Performance Computing. High performance computing systems are driving development and large-scale deployment of parallel optical interconnects to meet the ever-increasing interconnect bandwidth requirements. We have demonstrated generations of chip-scale transceivers, or “Optochips”, with record setting high-speed, high-density, […]
Interconnects Are Newest Twist in Intel vs. Arm
August 27, 2012 by
Over at EE Times, Rick Merritt writes that interconnects are the newest front in the war over server microprocessors between Intel and ARM. Intel is widely expected to implement in future Xeon processors the interconnect technology from a spate of recent acquisitions. Server and adapter makers believe such a move could narrow their hardware options […]
Performance Analysis of IB FDR and 40GigE RoCE on HPC and Cloud
August 26, 2012 by
httpv://www.youtube.com/watch?v=hQEXoUAyzDQ In this video, Jerome Vienne from Ohio State University presents: Performance Analysis and Evaluation of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems. In this paper, we evaluate various high performance interconnects over the new PCIe Gen3 interface with HPC as well as cloud computing workloads. Our comprehensive analysis, done at […]
Vectorizing Code on Sandy Bridge with AVX and SSE
August 26, 2012 by
Over at the Walking Randomly blog, Michael Croucher from the University of Manchester writes that there are many routes for programmers to take advantage of AVX vectorization on Sandy Bridge CPUs. Since working with intrinsics is such hard work, why not let the compiler take the strain? Many modern compilers can automatically vectorize your C, […]
Video: How SDNs Will Tame Networks
August 25, 2012 by
httpv://youtu.be/8Q9lSkGyQ84 In this video, Nick McKeown from Stanford presents: How SDNs Will Tame Networks. Networks are notoriously hard to debug. Today, we only have a rudimentary set of tools available, such as ping, traceroute, tcpdump, and netflow. These tools try to reconstruct the distributed state of the network in an ad-hoc fashion, while the state […]
Job of the Week: Research Staff Member and Postdoc in Exascale Research
August 25, 2012 by
The Deep Computing Systems Group at IBM’s T. J. Watson Research Center is seeking a Research Staff Member to work on development of future systems for compute intensive and data intensive applications. The Deep Computing Systems Group is heavily engaged in research to develop Esascale class systems for research, industrial and commercial use. The ideal […]
Chris Mattmann to Keynote HPC User Forum in Dearborn
August 24, 2012 by
This week IDC announced that Chris Mattmann from NASA JPL will keynote the next HPC User Forum meeting, Sept. 17-19 in Dearborn, Michigan. Mattman will describe his work on the International Square Kilometer Array telescope project, which is expected to generate 1PB of data per day when it becomes operational. The preliminary agenda for the HPC […]
PNNL Researchers Awarded Best Paper at IPDPS Symposium
August 24, 2012 by
Alessandro Morari and Roberto Gioiosa from Pacific Northwest National Laboratory won the best paper award at the recent International Parallel & Distributed Process Symposium in China. Their paper “Evaluating the Impact of TLB Misses on Future HPC Systems” presents a quantitative analysis of the effect of translation lookaside buffer misses on current and future parallel applications at scale. TLB […]
Video: Rx Stack Accelerator for 10 GbE Integrated NIC
August 24, 2012 by
httpv://www.youtube.com/watch?v=robu4XYxZ98 In this video, IBM’s François Abel presents: Rx Stack Accelerator for 10 GbE Integrated NIC. This paper describes the design of an integrated accelerator to offload computation intensive protocol-processing tasks. The accelerator combines the concepts of the transport-triggered architecture with a programmable finite-state machine to deliver high instruction-level parallelism, efficient multiway branching and flexibility. […]
