Nigel Stephens, Lead ISA Architect and ARM Fellow
Over at the ARM Community Blog, Nigel Stephens writes that the company has introduced scalable vector extensions (SVE) their A64 instruction set to bolster high performance computing.
In summary, SVE opens a new chapter for the ARM architecture in terms of the scale and opportunity for increasing levels of vector processing on ARM processor cores. It is early days for SVE tools and software, and it will take time for SVE compilers and the rest of the SVE software ecosystem to mature. HPC is the current focus and catalyst for this compiler work, and creates development momentum in areas such as Linux distributions and optimized libraries for SVE, as well as in ARM and third party tools and software. We are already engaging with key members of the ARM partnership, and will now broaden that engagement across the open-source community and wider ARM ecosystem to support development of SVE and the HPC market, enabling a path to efficient Exascale computing.
Key points about ARMv8-A SVE:
- ARM is significantly extending the vector processing capabilities associated with AArch64 (64-bit) execution in the ARM architecture, now and into the future, enabling implementation choices for vector lengths that scale from 128 to 2048 bits.
- High Performance Scientific Compute provides an excellent focus for the introduction of this technology and its associated ecosystem development.
- SVE features will enable advanced vectorizing compilers to extract more fine-grain parallelism from existing code and so reduce software deployment effort.
At the Hot Chips conference, today, Toshio Yoshida of Fujitsu described how SVE will be used in the Post-K supercomputer.
Fujitsu, as a lead provider has been collaborating closely with ARM and contributed to the development of the HPC extensions (called SVE) for ARMv8-A, a cutting edge ISA optimized for a wide range of HPC. Fujitsu is developing a new HPC processor conforming to ARMv8-A with SVE for the Post-K computer, based on our own microarchitecture, as used in our ongoing SPARC64 and mainframe processor development.”
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