PRACE Posts Best Practice Guide for Intel Xeon Phi

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The European PRACE initiative has published a new Best Practice Guide for Intel Xeon Phi, Knights Landing Edition.

Topics for the best practice guides includes: optimal porting of applications (e.g., choice of numerical libraries and compiler options); architecture-specific optimization and petascaling techniques; optimal system environment (e.g., tuneable system parameters, job placement and optimized system libraries); debuggers, performance analysis tools and programming environment.

“This best practice guide provides information about Intel’s MIC architecture and programming models for the Intel Xeon Phi co-processor in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-processor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications. The Knights Landing (KNL) processor differs from the usual Intel processor due to its very high core count and the hardware threading architecture. It represent an approach where a large number of simples cores are employed in large number as opposed to larger more sophisticated cores in smaller number. The idea is that a higher fraction of the transistors could be used for arithmetric operations. Over the decades the flops per transistor have declined. The KNL represent the second generation of this approach, the Knights Corner (KNC) being the first. There is also a best practice guide for the KNC.”

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