How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

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In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V.

Calista Redmond is CEO of the RISC-V Foundation.

We wanted to shine a spotlight on the European Processor Initiative (EPI), the project financed under the EU Horizon 2020 program, which has gathered together 26 partners from 10 European countries with the mission to develop and bring to market low power processor technology. The EPI consortium includes RISC-V Foundation members Barcelona Supercomputing Center (BSC), CEA, ETH Zurich, FORTH, Infineon and STMicroelectronics. The EPI project includes experts in the silicon and High Performance Computing (HPC) industries are collaborating to develop the first European HPC system-on-chips (SoCs) and accelerators, with the goal of creating a processor for the Exascale machine based on European technology. This Exascale supercomputer will be capable of one exaflop of performance –around a million times faster than typical desktop computers – which has the potential to significantly advance AI and scientific research.

When the EPI Consortium was approved in May 2018, European Commission leaders proclaimed that the project will help “develop an independent and innovative European supercomputing and data ecosystem” and “benefit Europe’s scientific leadership, industrial competitiveness, engineering skills and know-how and the society as whole.” In addition to focusing on solutions for the HPC market, the EPI project also targets the autonomous vehicles industry and the data center and servers market. As processing demands for these applications are skyrocketing – for example, as cars become more autonomous and capable of real-time decision making – novel silicon approaches are required to power the next generation of smart devices and machines.

As part of the EPI project, the Accelerator stream is working to develop and demonstrate European processor IPs based on the RISC-V instruction set architecture (ISA). The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”

For more background on the EPI, check out the program’s website.

In this video from the the 2018 RISC-V Workshop in Barcelona, Director Prof. Mateo Valero presents: European Processor Initiative & RISC-V.

To read more about the latest solutions developed by the EPI, check out news on the EPI website and the recent coverage from The Next Platform and Tom’s Hardware.

Bringing the industry a new level of free, extensible software and hardware freedom on architecture, the RISC-V ISA is opening up exciting new possibilities for innovation – especially for segments like HPC and AI that are undergoing compute disruption. The RISC-V Foundation has many work groups to further the open source technical progress of the ISA, including many key elements related to HPC. In addition, we have a Special Interest Group dedicated to collaboration of HPC interests. To learn more, please email

Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

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