Carey Kloss is Vice President and General Manager of Intel’s AI Training Products group.
In this Chip Chat podcast, Carey Kloss from Intel outlines the architecture and potential of the Intel Nervana NNP-T. He gets into major issues like memory and how the architecture was designed to avoid problems like becoming memory-locked, how the accelerator supports existing software frameworks like PaddlePaddle and TensorFlow, and what the NNP-T means for customers who want to keep on eye on power usage and lower TCO.
Deep learning workloads have evolved considerably over the last few years. Today’s models are larger, deeper, and more complex than neural networks from even a few years ago, with an explosion in size in the number of parameters per model. The Intel Nervana Neural Network Processor for Training (NNP-T) is a purpose-built deep learning accelerator to speed up the training and deployment of distributed learning algorithms.
Carey Kloss is Vice President and General Manager of Intel’s AI Training Products group, responsible for Intel’s AI-training specific training solutions. Carey holds a Bachelor of Science in Electrical and Computer Engineering and a Master of Science in Computer Engineering from Carnegie Mellon University.
