Aug. 20, 2024 — The Argonne Leadership Computing Facility will hold a webinar tomorrow from 11 am to noon Central Time covering chipStar, a HIP implementation for Aurora, the exascale-class supercomputer housed at Argonne.
Registration information can be found here.
ALCF Performance Engineering Team Lead Brice Videau will present chipStar, Argonne’s implementation of HIP, and an experimental implementation of CUDA for Intel GPUs.
chipStar architecture is based on the LLVM tool-chain targeting both OpenCL and Intel’s Level Zero. In this webinar, Videau will cover chipStar capabilities and limitations, instructions on how to build and run HIP with examples, and CUDA codes with chipStar on Aurora and Sunspot.
Videau is working on HPC-related topics such as heterogeneous platform programming and auto-tuning. He is also co-leading the Performance Engineering team at the ALCF.
