NICS Gets Faster Application Performance with the Cray® CS300™ Cluster Supercomputer Based on Intel® Xeon Phi™ Coprocessors

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In 2011, NICS set out to explore ways researchers could take advantage of emerging processing technologies. Prompted by the shift in the computing landscape to parallelism for meeting increasing performance needs, NICS researchers proposed to port and optimize scientific codes to the Intel Xeon Phi coprocessors based on the Intel® Many Integrated Core (MIC) architecture.
“In the past, adopting newer, faster processors has been the primary way scientists and engineers have achieved better application performance,” says Glenn Brook, CTO at the Joint Institute for Computational Sciences (JICS) at the University of Tennessee. “Today, they need to parallelize code and capitalize on the multiplication of processing cores for significant performance gains.”
Called the Beacon project, users would evaluate the performance of parallelized codes from a variety of fields — astrophysics to molecular dynamics to computational fluid dynamics — and ask what changes needed to be made to boost performance while minimizing associated costs. In order to carry out that work, they needed a development platform with the configuration flexibility to meet very specific needs.

Solution: Cray® CS300-AC™ cluster supercomputer

NICS needed to devise a single, experimental machine from the ground up that could enable a variety of different types of experiments.
“We’re not running one class of codes or problems here,” says Gregory Peterson, professor of electrical engineering at the University of Tennessee and project director at NICS. “You have a group that needs a large amount of memory, one that needs a tremendous amount of flops, another that needs something more balanced, and another limited by I/O-type performance. It was about the flexiblity to create an experimental machine that would allow users to explore.”

With funding from the National Science Foundation (NSF), NICS built “Beacon,” a Cray CS300-AC cluster supercomputer with 48 compute nodes and six I/O nodes joined with InfiniBand connectivity. “NICS has a strong relationship with Cray,” says Brook. “We knew that Cray could provide solid hardware, offer excellent support, and deliver systems on our accelerated timeline.”
The compute nodes are equipped with both Intel® Xeon® E5-2670 processors and Intel Xeon Phi coprocessors. In all, the cluster includes 768 conventional cores and 11,520 accelerator cores, delivering the hybrid environment NICS needed to explore a variety of programming and processing scenarios. Additionally, NICS configured Beacon with Intel SSDs and stepped up to 256 GB RAM per node (a large amount at the time), enabling them to explore data movement and new data paradigms as well as other paradigms of computational use. “One of the nice things about the cluster we built is that we have good performance but also big memory,” says Peterson. “[Beacon] can accommodate a very wide variety of workloads.”