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Video: System Interconnects for HPC

In this video from the 2017 Argonne Training Program on Extreme-Scale Computing, Pavan Balaji from Argonne presents an overview of system interconnects for HPC. “The Argonne Training Program on Extreme-Scale Computing (ATPESC) provides intensive, two weeks of training on the key skills, approaches, and tools to design, implement, and execute computational science and engineering applications on current high-end computing systems and the leadership-class computing systems of the future.”

HPC Network Stack on ARM

Pavel Shamis from ARM gave this talk at the MVAPICH User Group. “With the emerging availability HPC solutions based on ARM CPU architecture, it is important to understand how ARM integrates with the RDMA hardware and HPC network software stack. In this talk, we will overview ARM architecture and system software stack. We will discuss how ARM CPU interacts with network devices and accelerators. In addition, we will share our experience in enabling RDMA software stack and one-sided communication libraries (Open UCX, OpenSHMEM/SHMEM) on ARM and share preliminary evaluation results.”

Podcast: Intel Omni-Path adds Performance and Scalalability

“Intel OPA, part of Intel Scalable System Framework, is a high-performance fabric enabling the responsiveness, throughput, and scalability required by today’s and tomorrow’s most-demanding high performance computing workloads. In this interview, Misage talks about market uptake in Intel OPA’s first year of availability, reports on some of the first HPC deployments using the Intel Xeon Scalable platform and Intel OPA, and gives a sneak peek of what Intel OPA will be talking about at SC17.”

Advanced Clustering Technologies Deploys Lawrence Supercomputer at University of South Dakota

Today Advanced Clustering Technologies announced the deployment of a new supercomputer at the University of South Dakota. cluster. The machine is named “Lawrence” after Nobel Laureate and University of South Dakota alumnus E. O. Lawrence. “Lawrence makes it possible for us to accelerate scientific progress while reducing the time to discovery,” said Doug Jennewein, the University’s Director of Research Computing. “University researchers will be able to achieve scientific results not previously possible, and our students and faculty will become more engaged in computationally assisted research.”

Video: The Future of High Performance Interconnects

Ashrut Ambastha from Mellanox gave this talk at the HPC Advisory Council Australia conference. “Ashrut will review Co-Design collaborations with leaders in industry, academia, and manufacturing – and how they’re taking a holistic system-level approach to fundamental performance improvements expanding the capabilities of network as a new “co-processor” for handling and accelerating application workloads, dramatically improving application performance.”

Benefits of Multi-rail Cluster Architectures for GPU-based Nodes

Craig Tierney from NVIDIA gave this talk at the MVAPICH User Group meeting. “As high performance computing moves toward GPU-accelerated architectures, single node application performance can be between 3x and 75x faster than the CPUs alone. Performance increases of this size will require increases in network bandwidth and message rate to prevent the network from becoming the bottleneck in scalability. In this talk, we will present results from NVLink enabled systems connected via quad-rail EDR Infiniband.”

OCF Builds Isca Supercomputer for Life Sciences at University of Exeter

Researchers from across the University of Exeter can now benefit from a new HPC machine – Isca – that was configured and integrated by OCF to give the university a larger capacity for computational research. “We’ve seen in the last few years a real growth in interest in High-Performance Computing from life sciences, particularly with the availability of new high-fidelity genome sequencers, which have heavy compute requirements, and that demand will keep going up.”

Radio Free HPC Looks at High Performance Interconnects

In this podcast, the Radio Free HPC team looks at Dan’s recent talk on High Performance Interconnects. “When it comes to choosing an interconnect for your HPC cluster, what is the best way to go? Is offloading better than onloading? You can find out more by watching Dan’s talk from the HPC Advisory Council Australia conference.”

Video: DDN Burst Buffer

Justin Glen and Daniel Richards from DDN presented this talk at the HPC Advisory Council Australia Conference. “Burst Buffer was originally created to checkpoint-restart applications and has evolved to help accelerate applications & file systems and make HPC clusters more predictable. This presentation explores regional use cases, recommendations on burst buffer sizing and investment and where it is best positioned in a HPC workflow.”

OSC Hosts fifth MVAPICH Users Group

A broad array of system administrators, developers, researchers and students who share an interest in the MVAPICH open-source library for high performance computing will gather this week for the fifth meeting of the MVAPICH Users Group (MUG). “Dr. Panda’s library is a cornerstone for HPC machines around the world, including OSC’s systems and many of the Top 500,” said Dave Hudak, Ph.D., interim executive director of OSC. “We’ve gained a lot of insight and expertise from partnering with DK and his research group throughout the years.”