Over at the Intel Developer Zone, James Reinders writes that additional vector instructions have now been documented for Intel AVX-512, which will be first implemented in the future Intel Xeon Phi processor and coprocessor known by the code name Knights Landing.
These new instructions enrich the operations available as part of Intel AVX-512. These are provided in two groups. A group of byte and word (8 and 16-bit) operations known as Byte and Word Instructions, indicated by the AVX512BW CPUID flag, enhance integer operations. It is notable that these do make use of all 64 bits in the mask registers. A group of doubleword and quadword (32 and 64-bit) operations known as Doubleword and Quadword Instructions, indicated by the AVX512DQ CPUID flag, enhance integer and floating-point operations.
Intel AVX-512 instructions represent a significant leap to 512-bit SIMD support. Programs can pack eight double precision or sixteen single precision floating-point numbers, or eight 64-bit integers, or sixteen 32-bit integers within the 512-bit vectors. This enables processing of twice the number of data elements that AVX/AVX2 can process with a single instruction and four times that of SSE.
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