In this video, Intel’s James Reinders and Vadim Karpusenko from Colfax International discuss the future of parallel programming and Intel MIC architecture products: Intel Xeon Phi coprocessors, Knights Landing (KNL), and forthcoming 3rd generation – Knight Hill (KNH). They also describe how students can learn parallel programming and optimization of high performance applications.
- James Reinders and his role at Intel. – 00:47
- Why Parallel Programming and Code Modernization is important? – 01:49
- Brief introduction to MIC architecture and Xeon Phi coprocessors. – 04:03
- What type of applications benefit from MIC architecture? – 07:16
- How to approach porting your code for MIC architecture? – 09:58
- What is new in Knights Landing. – 15:24
- Details of chip design of Knights Landing. – 19:54
- 3rd MIC generation – Knights Hill. – 21:16
- How to future-proof my code? – 23:15
- High bandwidth memory on KNL. – 27:35
- Details on James Reinders’ books. – 29:59
- Future of Parallel Programming. – 34:37
- New parallel programming languages? – 38:16
- Future of the parallel libraries. – 40:01
- How to learn parallel programming? – 45:22
- Colfax Developer Training. – 48:20
In related news, Intel is offering an updated and expanded series of software developer training sessions on parallel programming using the Intel Xeon Phi coprocessor.
This series of offerings provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel Xeon processors and Intel Xeon Phi coprocessors. The courses contain materials and practical exercises appropriate for developers beginning their journey to parallel programming, as well as provide cutting-edge detail to HPC experts on the best practices for Intel’s multicore and many-core architectures and software development tools. The offerings include a one-day introductory lecture (free), a one-day hands-on laboratory (free), and a four-day immersive workshop.