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Video: State of ARM-based HPC

Paul Isaacs from Linaro

In this video, Paul Isaacs from Linaro presents: State of ARM-based HPC. This talk provides an overview of applications and infrastructure services successfully ported to Aarch64 and benefiting from scale.

With its debut on the TOP500, the 125,000-core Astra supercomputer at New Mexico’s Sandia Labs uses Cavium ThunderX2 chips to mark Arm’s entry into the petascale world. In Japan, the Fujitsu A64FX Arm-based CPU in the pending Fugaku supercomputer has been optimized to achieve high-level, real-world application performance, anticipating up to one hundred times the application execution performance of the K computer. K was the first computer to top 10 petaflops in 2011.

The world’s fastest 500 computers run Linux-based operating systems and thus, HPC relies on Open Source. HPC has a large and growing open source component. Toolchains can be offered to those who want a choice and engineering can be focused on library optimization that will benefit all micro architectures. Linaro provides a forum where SoCs, system vendors, integrators, users, distros, hyperscalers can co-develop the foundational software necessary for the ecosystem.

Linaro and its members created the HPC Special Interest Group (SIG) in 2016 to drive the adoption of Arm in HPC through standardization, interoperability, orchestration and use case development. The HPC SIG is currently working to leverage Arm hardware around server class infrastructure, multi-gigabit interconnect support, scalable vector extensions and software ecosystem support to build exascale HPC deployments. The engineering focus is on OpenHPC, compiler performance,SVE enablement and hardware deployment.

  • OpenHPC: Fully automating OpenHPC CI & releases and deploying dynamic clusters on varied vendors/hardware configurations/OS distros
  • Compiler performance: Running a variety of HPC benchmarks for CPU-bound issues and detecting common outliers for bottlenecks
  • SVE enablement: Improving SVE support in GCC for more vectorization cases, enabling LLVM to generate SVE code, and finishing (and upstreaming) QEMU support
  • Hardware deployment: Work in Linaro’s own HPC lab for best-in-class stability & repeatability, close-to-production ennironment, upstream technology, vendor isolation.

Paul Isaacs is Technical Lead for HPC-SIG within Linaro’s Datacenter & Cloud Group. He has 30+ years of international infrastructure architecture experience from Smart NICs to HPC and software development.

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