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TSMC Debuts FINFLEX, N2 Process

SANTA CLARA, CA, Jun. 16, 2022 – TSMC today showcased its advanced logic, specialty and 3D IC technologies at the company’s 2022 North America Technology Symposium, with the next-generation N2 process utilizing nanosheet transistors and the FINFLEX technology for the N3 and N3E processes making their debuts.

Highlighted at the symposium:

TSMC’s N3 technology, set to enter volume production later in 2022, will have the TSMC FINFLEX architectural feature offering what the company said is “unparalleled flexibility for designers,” including choices of different standard cells with a 3-2 fin configuration for ultra performance, a 2-1 fin configuration for power efficiency and transistor density, and a 2-2 fin configuration intended to provide a balance between the two. “With TSMC FINFLEX architecture, customers can create system-on-chip designs precisely tuned for their needs with functional blocks implementing the best optimized fin configuration for the desired performance, power and area target, and integrated on the same chip.

TSMC’s N2 technology offers a 10-15 percent speed improvement at the same power over N3, or 25-30 percent power reduction at the same speed, according to the company. “N2 will feature nanosheet transistor architecture to deliver a full-node improvement in performance and power efficiency…,” TSMC said. “The N2 technology platform includes a high-performance variant in addition to the mobile compute baseline version, as well as comprehensive chiplet integration solutions.” N2 is scheduled to begin production in 2025.

Building on the N12e technology, TSMC is developing N6e, process technology designed to provide the computing power and energy efficiency required by edge AI and IoT devices. N6e will be based on TSMC’s advanced 7nm process and is expected to have three times greater logic density than N12e. It will serve as a part of TSMC’s Ultra-Low Power platform, a portfolio of logic, RF, analog, embedded nonvolatile memory and power management IC solutions aimed at applications in edge AI and the Internet of Things, according to TSMC.

TSMC is showcasing two customer applications of the TSMC-SoIC chip stacking solution:

  1. What TSMC said is the first SoIC-based CPU employing Chip-on-Wafer (CoW) technology to stack SRAM as a Level 3 cache.
  2. An intelligence processing unit stacked on top of a deep trench capacitor die using Wafer-on-Wafer (WoW) technology.

With N7 chips in production for both CoW and WoW, support for N5 technology is scheduled for 2023, TSMC said. The company also said to support SoIC and other TSMC 3DFabric system integration services, “the world’s first fully automated 3DFabric factory is set to begin production in the second half of 2022.”

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