In this Intel Chip Chat podcast, Alyson Klein and Charlie Wuischpard describe Intel’s investment to break down walls to HPC adoption and move innovation forward by thinking at a system level. “Charlie discusses the announcement of the Intel Xeon Phi processor, which is a foundational element of Intel Scalable System Framework (Intel SSF), as well as Intel Omni-Path Fabric. Charlie also explains that these enhancements will make supercomputing faster, more reliable, and increase efficient power consumption; Intel has achieved this by combining the capabilities of various technologies and optimizing ways for them to work together.”
In this Intel Chip Chat podcast with Allyson Klein, Cray CTO Steve Scott describes the collaboration between Cray and Intel on the Intel Xeon Phi Processor for supercomputer integration. Steve highlights that Cray chose to implement the new Intel Xeon Phi Processor for its supercomputers because of the potential to support a diverse array of customer needs and deliver the best performance per application. He emphasizes that Cray software tools are key to optimizing Intel Xeon Phi processor performance at the system level.
Offloading to a coprocessor does need to be considered carefully, due to the memory transfer requirements. When the data that is to be worked on resides in the memory of the main system, that data must be transferred to the coprocessor’s memory. The challenge arises because memory is not physically shared between the main system and the coprocessor.
“There are two offload models that the developer must consider when programming an application. The first is the non-shared memory model, and the second is the virtual shared memory model. Both of these models can be used in the same application.”
For decades, Intel has been enabling insight and discovery through its technologies and contributions to parallel computing and High Performance Computing (HPC). Central to the company’s most recent work in HPC is a new design philosophy for clusters and supercomputers called Intel® Scalable System Framework (Intel® SSF), an approach designed to enable sustained, balanced performance as the community pushes towards the Exascale era.
The Argonne Leadership Computing Facility (ALCF) is now accepting proposals for its Aurora Early Science Program (ESP) through September 2, 2016. The program will award computing time to 10 science teams to pursue innovative research as part of pre-production testing on the facility’s next-generation system. Aurora is a massively parallel, many-core Intel-Cray supercomputer that will deliver 18 times the computational performance of Mira, ALCF’s current production system.
Today, Allinea announced that the company will be exhibiting at XSEDE16 July 17-21 in Miami. The conference will attract an audience across industry and academia to discuss the key themes of diversity, big data and science at scale. “Our tools are used extensively across the XSEDE user base so we’re delighted to be extending the value they bring by giving practical advice for getting the best out of infrastructure capabilities through software tuning, especially given the addition of support for the full Intel Xeon Phi family in our new v6.1 software release,” said Rob Rick, VP Americas for Allinea.”
The Intel HPC Developer Conference has issued its Call for Proposals. Held in conjunction with SC16, the event takes place Nov. 12-13 in Salt Lake City.
NASA Ames reports that SGI has completed an important upgrade to Pleiades supercomputer. “As of July 1, 2016, all of the remaining racks of Intel Xeon X5670 (Westmere) processors were removed from Pleiades to make room for an additional 14 Intel Xeon E5-2680v4 (Broadwell) racks, doubling the number of Broadwell nodes to 2,016 and increasing the system’s theoretical peak performance to 7.25 petaflops. Pleiades now has a total of 246,048 CPU cores across 161 racks containing four different Intel Xeon processor types, and provides users with more than 900 terabytes of memory.”
Intel® Cilk™ Plus is an extension to C and C++ that offers a quick and easy way to harness the power of both multicore and vector processing. The three Intel Cilk Plus keywords provide a simple yet surprisingly powerful model for parallel programming, while runtime and template libraries offer a well-tuned environment for building parallel applications.
An eye-popping visualization of two black holes colliding demonstrates 3D Adaptive Mesh Refinement volume rendering on next-generation Intel® Xeon Phi™ processors. “It simplifies things when you can run on a single processor and not have to offload the visualization work,” says Juha Jäykkä, system manager of the COSMOS supercomputer. Dr. Jäykkä holds a doctorate in theoretical physics and also serves as a scientific consultant to the system’s users. “Programming is easier. The Intel Xeon Phi processor architecture is the next step for getting more performance and more power efficiency, and it is refreshingly convenient to use.”