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Vectorization Steps

The process to vectorize application code is very important and can result in major performance improvements when coupled with vector hardware. In many cases, incremental work can mean a large payoff in terms of performance. “When applications that have successfully been implemented on supercomputers or have made use of SIMD instructions such as SSE or AVX are excellent candidates for a methodology to take advantage of modern vector capabilities in servers today.”

Ansys SeaHawk Brings Big Data Analytics to EDA

Ansys, a provider of engineering simulation technology, has announced the release of its SeaScape architecture to help engineers accelerate the optimization of designs using a combination of elastic computation, machine learning, big data analytics and simulation technology.

Sri Sathya Sai Institute in India Chooses Bright Technology

Today Bright Computing announced that Sri Sathya Sai Institute of Higher Learning (SSSIHL) in India has chosen Bright infrastructure management technology to manage its HPC environment. This heterogeneous and hybrid cluster at SSSIHL is the first step towards achieving a self-sufficient HPC facility for the Institute’s research work, and we are pleased that Bright is […]

Disruptive Opportunities and a Path to Exascale: A Conversation with HPC Visionary Alan Gara of Intel

“We want to encourage and support that collaborative behavior in whatever way we can, because there are a multitude of problems in government agencies and commercial entities that seem to have high performance computing solutions. Think of bringing together the tremendous computational expertise you find from the DOE labs with the problems that someone like the National Institutes of Health is trying to solve. You couple those two together and you really can create something amazing that will affect all our lives. We want to broaden their exposure to the possibilities of HPC and help that along. It’s important, and it will allow all of us in HPC to more broadly impact the world with the large systems as well as the more moderate-scale systems.”

Cray Urika-GX System to Tackle Big Data Analytics

“We took the Aries system interconnect from our supercomputers, the industry-standard architecture of our clusters, the scalable graph engine from the Urika-GD appliance, and the pre-integrated, open infrastructure of our Urika-XA system and combined them into one agile analytics platform. The Urika-GX gives our customers the tool they need to overcome their most advanced analytics challenges today, and the platform to bridge to tomorrow.”

Satoshi Matsuoka Presents: The Inevitable End of Moore’s Law

“The promising new parameter in place of the transistor count is the perceived increase in the capacity and bandwidth of storage, driven by device, architectural, as well as packaging innovations: DRAM-alternative Non-Volatile Memory (NVM) devices, 3-D memory and logic stacking evolving from VIAs to direct silicone stacking, as well as next-generation terabit optics and networks. The overall effect of this is that, the trend to increase the computational intensity as advocated today will no longer result in performance increase, but rather, exploiting the memory and bandwidth capacities will instead be the right methodology.”

Video: The Vital Importance of HPC to U.S. Competitiveness and National Security

In this video, ITIF hosts a hearing on the The Vital Importance of High-Performance Computing to U.S. Competitiveness and National Security. Their recently published report urges U.S. policymakers to take decisive steps to ensure the United States continues to be a world leader in high-performance computing.

Using Vectors on Intel Xeon Phi

The use of vector instructions can speed up applications tremendously when used correctly. The benefit is that much more work can be done in a clock cycle than by performing the operation one at a time. The Intel Xeon Phi coprocessor was designed with strong support for vector level parallelism. “When these techniques are used either individually or in combination in different areas of the application, the performance will surely be increased, in many cases without a lot of effort.”

Video: Lustre Update from Seagate Technologies

Peter Bojanic presented this talk at LUG 2016 in Portland. “At LUG 2016, Seagate announced it will incorporate Intel Enterprise Edition for Lustre (IEEL), a big data software platform, into its market-leading ClusterStor storage architecture for high-performance computing. The move will strengthen Seagate’s HPC data storage product line and provide customers with an additional choice of Lustre parallel file systems to help drive advancements in the HPC and big data market.”

Radio Free HPC News Roundup for Friday the 13th

In this podcast, the Radio Free HPC team looks at the news highlights for the week leading up to Friday the 13th of May, 2016. Highlights include a 25 Petaflop Fujitsu supercomputer coming to Japan, an OpenPOWER Summit coming to Europe, and fighting the Zombie Apocalypse with HPC.