“The complexity and high costs of architecting and maintaining streaming analytics solutions often make it difficult to get new projects off the ground. That’s part of the reason Kx, a leading provider of high-volume, high-performance databases and real-time analytics solutions, is always interested in exploring how new technologies may help it push streaming analytics performance and efficiency boundaries. The Intel Xeon Phi processor is a case in point. At SC16 in Salt Lake City, Kx used a 1.2 billion record database of New York City taxi cab ride data to demonstrate what the Intel Xeon Phi processor could mean to distributed big data processing. And the potential cost/performance implications were quite promising.”
“Phase one at CINECA, an academic consortium, was completed in May 2016 – coming in at 1.7 Petaflops, which at the time it was the largest Intel Omni-Path Fabric system in the world. Lenovo and CINECA are pleased to announce the delivery and installation of phase two, a 3,600 node Intel Xeon Phi processor which is interconnected with 100Gb Intel Omni-Path fabric – delivering 6.2 Petaflops of performance.”
“Software Defined Visualization (SDVis) is an open source initiative from Intel and industry collaborators to improve the visual fidelity, performance and efficiency of prominent visualization solutions – with a particular emphasis on supporting the rapidly growing “Big Data” usage on workstations through HPC supercomputing clusters without the memory limitations and cost of GPU based solutions. Existing applications can be enhanced using the high performing parallel software rendering libraries OpenSWR, Embree, and OSPRay. At the Intel HPC Developer Conference, Amstutz provided an introduction to this initiative, its benefits, a brief descriptions of accomplishments in the past year and talk about the changes made to Intel provided libraries in the past year.”
“When designing an application that contains many threads and less cores than threads, it is important to understand what is the optimal number of threads that should be assigned to a core. This value should be parameterized, in order to easily run tests to determine which is the optimum value for a given machine. One thread per core on the Intel Xeon Phi processor will give the highest performance per thread. When the number of threads per core is set at two or four, the individual thread performance may be lower, but the aggregate performance will be greater.”
“As seen at installations included on both the Green500 and Top500 lists, Asetek’s distributed liquid cooling architecture enables cluster energy efficiency in addition to sustained and un-throttled cluster performance,” said John Hamill, Vice President of WW Sales and Marketing. “Around the world, data centers are increasingly using Asetek technology for High Performance Computing while reducing energy costs.”
Today the Barcelona Supercomputing Center announced plans to MareNostrum 4, a 13.7 Petaflop supercomputer that will be 12.4 times more powerful than the current MareNostrum 3 system. In a contract valued at almost €30 million, IBM will integrate in one sole machine using its own technologies alongside those of Lenovo, Intel, and Fujitsu.
“Intel HPC Orchestrator simplifies the installation, management, and ongoing maintenance of an HPC system by reducing the amounft of integration and validation effort required to run an HPC system software stack. With Intel HPC Orchestrator, based on the OpenHPC system software stack, you can take advantage of the innovation driven by the open source community – while also getting peace of mind from Intel® support across the HPC system software stack.”
As data center sprawl is now understood to be expensive and may not deliver performance increases for all types of applications, new technologies are coming to the rescue. A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence “field-programmable”. While the use of GPUs and HPC accelerators are generally understood today, there are a number of misconceptions about FPGAs that need to be understood.
Today Russia’s RSC Group announced that the company has achieved a record compute density of 1.41 Pflops per rack using direct liquid cooling and Intel Xeon Phi processors. “RSC supported the TUM student team from Munich with 8 nodes mobile cluster based on RSC Tornado direct liquid cooled architecture. This computing system provided stable operation of computing nodes in “hot water” mode at +63 °С cooling agent temperature at node inputs and had the following configuration: 72-cores Intel Xeon Phi 7290 processors, Intel S7200AP server boards, Intel SSD DC S3500 Series M.2 340 GB solid-state drives, switch and adapters based on Intel Omni-Path high-speed fabric, highly efficient Micron DDR4-2400 VLP 16-32 GB memory modules.”
In this video from the Intel HPC Developer Conference, Akira Sano from Supermicro describes the company’s Machine Learning Solutions on Intel Architecture. “Our server systems, subsystems and accessories are architecturally designed to provide high levels of reliability, quality and scalability, thereby enabling our customers benefits in the areas of compute performance, density, thermal management and power efficiency to lower their overall total cost of ownership.”