The Penn State Cyber-Laboratory for Astronomy, Materials, and Physics (CyberLAMP) is acquiring a high-performance computer cluster that will facilitate interdisciplinary research and training in cyberscience and is funded by a grant from the National Science Foundation. The hybrid computer cluster will combine general purpose central processing unit (CPU) cores with specialized hardware accelerators, including the latest generation of NVIDIA graphics processing units (GPUs) and Intel Xeon Phi processors.
“As with all new technology, developers will have to create processes in order to modernize applications to take advantage of any new feature. Rather than randomly trying to improve the performance of an application, it is wise to be very familiar with the application and use available tools to understand bottlenecks and look for areas of improvement.”
DK Panda from Ohio State University presented this deck at the 2017 HPC Advisory Council Stanford Conference. “This talk will focus on challenges in designing runtime environments for exascale systems with millions of processors and accelerators to support various programming models. We will focus on MPI, PGAS (OpenSHMEM, CAF, UPC and UPC++) and Hybrid MPI+PGAS programming models by taking into account support for multi-core, high-performance networks, accelerators (GPGPUs and Intel MIC), virtualization technologies (KVM, Docker, and Singularity), and energy-awareness. Features and sample performance numbers from the MVAPICH2 libraries will be presented.”
In this video from KAUST Live: Patricia Damkroger discusses her new role as Vice President, Data Center Group and General Manager, Technical Computing Initiative, Enterprise and Government at Intel. “As the former Associate Director for Computation at Lawrence Livermore National Laboratory (LLNL), Trish Damkroger lead the 1,000-employee workforce behind the Laboratory’s high performance computing efforts. She is a longtime committee member and one-time general chair of the SC conference. Most recently, Damkroger was the SC16 Diverse HPC Workforce Chair.”
The European PRACE initiative has published a new Best Practice Guide for Intel Xeon Phi, Knights Landing Edition. “This best practice guide provides information about Intel’s MIC architecture and programming models for the Intel Xeon Phi co-processor in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-processor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications.”
In this video, researchers describe how the Tianhe-1 supercomputer supports scientific research. “Currently #43 on the TOP500, the 2.56 Petaflop Tianhe-1A carries out 1,400 computing tasks per day. It is mainly used to serve universities, research institutions, small and medium-sized enterprises, and provide scientific computing services.”
Applications that can take advantage of the new vectorization capabilities of the Intel Xeon Phi processor will show tremendous performance gains. “When considering vectorization, there are different tools that can assist the developer in determining where to look further. The first is to look at the optimization reports that are generated by the Intel compiler and then to also use the Vector Analyzer that can give specific advice on what to do to get more vectorization from the code.”
In this video from SUSECON 2016, Jo Harris from SUSE sits down with Dr. Figen Ulgen, GM HPC Software and Cloud at Intel to discuss women in Open Source and HPC, how Intel is contributing to this initiative, and the need for more women in the field.
Argonne has selected 10 computational science and engineering research projects for its Aurora Early Science Program starting this month. Aurora, a massively parallel, manycore Intel-Cray supercomputer, will be ALCF’s next leadership-class computing resource and is expected to arrive in 2018. The Early Science Program helps lay the path for hundreds of other users by doing actual science, using real scientific applications, to ready a future machine. “As with any bleeding edge resource, there’s testing and debugging that has to be done,” said ALCF Director of Science Katherine Riley.
Today Intel announced record results on a new benchmark in deep learning and convolutional neural networks (CNN). ZTE’s engineers used Intel’s midrange Arria 10 FPGA for a cloud inferencing application using a CNN algorithm. “ZTE has achieved a new record – beyond a thousand images per second in facial recognition – with what is known as “theoretical high accuracy” achieved for their custom topology. Intel’s Arria 10 FPGA accelerated the raw design performance more than 10 times while maintaining the accuracy.”