In this Texas Standard podcast, Dan Stanzione from TACC describes Stampede2, the most powerful university supercomputer in the United States. “Phase 1 of the Stampede2 rollout, now complete, features 4,200 Knights Landing (KNL) nodes, the second generation of processors based on Intel’s Many Integrated Core (MIC) architecture. Later this summer Phase 2 will add 1,736 Intel Xeon Skylake nodes.”
Boosting Manycore Code Optimization Efforts with Roofline Technology
May 2, 2017 by
A software toolkit developed at Berkeley Lab to better understand supercomputer performance is now being used to boost application performance for researchers running codes at NERSC and other supercomputing facilities. “Since its initial development, what is now known as the Empirical Roofline Toolkit (ERT) has benefitted from contributions by several Berkeley Lab staff. Along the way, HPC users who write scientific applications for manycore systems have been able to apply the toolkit to their applications and see how changing parameters of their code can improve performance.”
NERSC Selects Six Teams for Exascale Science Applications Program
January 19, 2017 by
Following a call for proposals issued last October, NERSC has selected six science application teams to participate in the NERSC Exascale Science Applications Program for Data (NESAP for Data) program. “We’re very excited to welcome these new data-intensive science application teams to NESAP,” said Rollin Thomas, a big data architect in NERSC’s Data Analytics and Services group who is coordinating NESAP for Data. “NESAP’s tools and expertise should help accelerate the transition of these data science codes to KNL. But I’m also looking forward to uncovering and understanding the new performance and scalability challenges that are sure to arise along the way.”
Cray Adds Intel Xeon Phi Processor to Flagship Line of Supercomputers
June 21, 2016 by
Today Cray introduced new performance breakthroughs that will provide customers with the fastest Cray XC supercomputers and Cray Sonexion storage systems to date. “Our customers are taking on increasingly complex computational problems that are expanding the boundaries of supercomputing and storage performance capabilities,” said Ryan Waite, Cray’s senior vice president of products. “We partner closely with our customers to understand their unique requirements and deliver new systems that deliver peak performance. For many of our customers, Intel Xeon Phi processors and Lustre parallel file systems are critical components of their supercomputing infrastructure. Our close collaboration with Intel helps to ensure our Intel Xeon Phi processor-based solutions scale to the most demanding performance requirements and our close partnership with Seagate helps scale Lustre to new levels of performance and stability.”
New Developer Platform to Accelerate Adoption of Knights Landing
June 15, 2016 by
With the release of a Developer Access Program for the Intel Xeon Phi Processor codenamed Knights Landing, Intel and its partner Colfax are widening early levels of access, support and training for the widely anticipated next-generation Intel Xeon Phi processor release. The Developer Access Program gives developers the opportunity to begin leveraging key new capabilities in the processor before they are generally available. That means developers will have time to work to parallelize and vectorize their code and look for opportunities to exploit the massive performance capabilities that KNL offers so workloads are ready for prime time when customers deploy their next-generation systems.
Stampede 2 Supercomputer at TACC to Sport 18 Petaflops
June 2, 2016 by
Over at the Dell HPC Community, Jim Ganthier writes that TACC is planning to deploy its 18 Petflop Stampede 2 supercomputer based on Dell servers running Intel Knights Landing processors. “Stampede 2 will do more than just meet growing demand from those who run data-intensive research. Imagine the discoveries that will be made as a result of this award and the new system. Now more than ever is an exciting time to be in HPC.”
