“How can quants or financial engineers write financial analytics libraries that can be systematically efficiently deployed on an Intel Xeon Phi co-processor or an Intel Xeon multi-core processor without specialist knowledge of parallel programming? A tried and tested approach to obtaining efficient deployment on many-core architectures is to exploit the highest level of granularity of parallelism exhibited by an application. However, this approach may require exploiting domain knowledge to efficiently map the workload to all cores. Using representative examples in financial modeling, this talk will show how the use of Our Pattern Language (OPL) can be used to formalize this knowledge and ensure that the domains of concerns for modeling and mapping the computations to the architecture are delineated. We proceed to describe work in progress on an Intel Xeon Phi implementation of Quantlib, a popular open-source quantitative finance library.”
Video: Designing Parallel Financial Analytics Libraries Using a Pattern Oriented Approach
Video: Diving into Intel’s HPC Scalable System Framework Plans
“In July, Intel announced plans for the HPC Scalable System Framework – a design foundation enabling wide range of highly workload-optimized solutions. This talk will delve into aspects of the framework and highlight the relationship and benefits to application development and execution.”
Video: SDVis Overview & OpenSWR – A Scalable High Performance Software Rasterizer for SCIVIS
In this video from the Intel HPC Developer Conference at SC15, Jim Jeffers from Intel presents an SDVis Overview. After that, Bruce Cherniak from Intel presents: OpenSWR: Fast SW Rendering within MESA. “This session has two talk for the price of one: (1) Software Defined Visualization: Modernizing Vis. A ground swell is underway to modernize HPC codes to take full advantage of the growing parallelism in today’s and tomorrow’s CPU’s. Visualization workflows are no exception and this talk will discuss the recent Software Defined Visualization efforts by Intel and Vis community partners to improve flexibility, performance and workflows for visual data analysis and rendering to maximize scientific understanding. (2) OpenGL rasterized rendering is a so called “embarrasingly” parallel workload. As such, multicore and manycore CPUs can provide strong, flexible and large memory footprint solutions, especially for large data rendering. OpenSWR is a MESA3D based parallel OpenGL software renderer from Intel that enables strong interactive performance for HPC visualization applications on workstations through supercomputing clusters without the I/O and memory limitations of GPUs. We will discuss the current feature support, performance and implementation of this open source OpenGL solution.”
Video: Scientific Insights and Discoveries through Scalable HPC at LRZ
In this video from the Intel HPC Developer Conference at SC15, Prof. Dieter Kranzlmüller from LRZ presents: Scientific Insights and Discoveries through Scalable High Performance Computing at LRZ. “Science and research today relies heavily on IT-services for discoveries and breakthroughs. The Leibniz Supercomputing Centre (LRZ) is a leading provider of scalable high performance computing and other services for researchers in Munich, Bavaria, Germany, Europe and beyond. This talk describes the LRZ and its services for the scientific community, providing an overview of applications and the respective technologies and services provided by LRZ. At the core of its services is SuperMUC, a highly scalable supercomputer using hot water cooling, which is one of the world’s most energy-efficient systems.
Video: Rendering in Ensight with OpenSWR
“EnSight is a software program for visualizing, analyzing, and communicating data from computer simulations and/or experiments. The purpose of OpenSWR is to provide a high performance, highly scalable OpenGL compatible software rasterizer that allows use of unmodified visualization software. This allows working with datasets where GPU hardware isn’t available or is limiting. OpenSWR is completely CPU-based, and runs on anything from laptops, to workstations, to compute nodes in HPC systems. OpenSWR internally builds on top of LLVM, and fully utilizes modern instruction sets like Intel®Streaming SIMD Extensions (SSE), and Intel® Advanced Vector Extensions (AVX and AVX2) to achieve high rendering performance.”
Video: High Performance Clustering for Trillion Particle Simulations
“Modern Cosmology and Plasma Physics codes are capable of simulating trillions of particles on petascale systems. Each time step generated from such simulations is on the order of 10s of TBs. Summarizing and analyzing raw particle data is challenging, and scientists often focus on density structures for follow-up analysis. We develop a highly scalable version of the clustering algorithm DBSCAN and apply it to the largest particle simulation datasets. Our system, called BD-CATDS, is the first one to perform end-to-end clustering analysis of trillion particle simulation output. We demonstrate clustering analysis of a 1.4 Trillion particle dataset from a plasma physics simulation, and a 10,240^3 particle cosmology simulation utilizing ~100,000 cores in 30 minutes. BD-CATS has enabled scientists to ask novel questions about acceleration mechanisms in particle physics, and has demonstrated qualitatively superior results in cosmology. Clustering is an example of one scientific data analytics problem. This talk will conclude with a broad overview of other leading data analytics challenges across scientific domains, and joint efforts between NERSC and Intel Research to tackle some of these challenges.”
Hewlett Packard Enterprise Showcases Benefits of Code Modernization
“We’ve tailored our story for the HPC developers here, who are really worried about applications and performance of applications. What’s really happened traditionally is that the single-threaded applications had not really been able to take advantage of the multi-core processor-based server platforms. So they’ve not really been getting the optimized platform and they’ve been leaving money on the table, so to speak. Because when you can optimize your applications for parallelism, you can take advantage of these multi-processor server platform. And you can get sometimes up to 10x performance boost, maybe sometime 100x, we’ve seen some financial services applications, or 3x for chemistry types of simulations as an example.”
Podcast: Intel HPC Developer Conference Coming to Austin for SC15
In this podcast, Intel Software Evangelist James Reinders describes the upcoming Intel HPC Developer Conference. Featuring a keynote by Jack Dongarra from the University of Tennessee, the event takes place Nov. 14-15 in Austin, just prior to SC15. “Modernizing your code on Intel architecture can help you achieve breakthrough performance for highly parallel applications. And, you won’t have to recode your entire problem, or master new tools and programming models.”
Intel HPC Developer Conference Coming to SC15
The first annual Intel HPC Developer Conference is coming to Austin Nov. 14-15 in conjunction with SC15. “The Intel® HPC Developer Conference will bring together developers from around the world to discuss code modernization in high performance computing. Learn what’s next in HPC, its technologies, and its impact on tomorrow’s innovations. Find the solutions to your biggest challenges at the Intel® HPC Developer Conference.”
