June 12, 2024 — Chip and silicon IP provider Rambus today announced the launch of its PCI Express(PCIe) 7.0 IP portfolio, a suite of IP solutions including: PCIe 7.0 Controller designed to deliver the high bandwidth, low latency, and robust performance required for next-generation AI and HPC applications PCIe 7.0 Retimer for highly-optimized, low-latency data […]
Rambus Launches 5600 MT/s RCD Chip for DDR5 Memory Module Suppliers
October 13, 2021 by
SAN JOSE, Oct. 13, 2021 — Rambus Inc. (NASDAQ: RMBS), a chip and silicon IP provider, today announced it is sampling its 5600 MT/s 2nd-generation RCD chip to the major DDR5 memory module (RDIMM) suppliers. This new level of performance represents a 17 percent increase in data rate over the first-generation 4800 MT/s Rambus DDR5 RCD. With key […]
Avery Design Systems and Rambus Extend Memory Model and PCIe VIP Collaboration
May 19, 2021 by
Tewksbury, MA. and San Jose – May 19, 2021 – Avery Design Systems, maker of functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of chips and silicon IP designed to make data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to […]
Rambus Launches 800G MACsec Multi-Channel Engine
April 30, 2020 by
Today Rambus announced its 800G MACsec (Media Access Control security) solution for next-generation networking infrastructure. The 800G MACsec solution delivers hardware-based, point-to-point security for 800 Gigabit Ethernet links and is a critical element of end-to-end network security. “Our 800G MACsec protocol engine leverages a scalable architecture that supports configurations of one to many ports with an aggregate bandwidth of up to 800 Gbps. This flexibility provides the benefit of limiting the silicon cost for security, while safeguarding required data communications.”
Video: High-Performance Memory For AI And HPC
April 5, 2020 by
In this video, Frank Ferro from Rambus examines the current performance bottlenecks in HPC, drilling down into power and performance for different memory options. “HBM2E offers the capability to achieve tremendous memory bandwidth. Four HBM2E stacks connected to a processor will deliver over 1.6 TB/s of bandwidth. And with 3D stacking of memory, high bandwidth and high capacity can be achieved in an exceptionally small footprint. Further, by keeping data rates relatively low, and the memory close to the processor, overall system power is kept low.”
Video: Big Data is Dead, Long Live Its Replacement
August 16, 2019 by
Tom Fisher gave this talk at the Samsung Forum. “Big Data is experiencing a second revolution. This talk will address what’s happened, how it happened and what big data is bridging too. Enterprise companies have to make business critical decisions in the coming years and the marketplace is not clear. The recent changes in the Big Data market will be reviewed as well as the effects on the related ecosystem. The goal of this presentation is to provide insights to engineers, data engineers and data scientists to better navigate a rapidly moving landscape.”
Radio Free HPC Looks at Diverging Chip Architectures in the Wake of Spectre and Meltdown
February 13, 2018 by
In this podcast, the Radio Free HPC team looks at the tradeoff between chip performance and security. In the aftermath of the recently disclosed Spectre and Meltdown exploits, Cryptograpy guru Paul Kocher from Rambus is calling for a divergence in processor architectures:
Rambus Collaborates with Microsoft on Cryogenic Memory
April 18, 2017 by
“With the increasing challenges in conventional approaches to improving memory capacity and power efficiency, our early research indicates that a significant change in the operating temperature of DRAM using cryogenic techniques may become essential in future memory systems,” said Dr. Gary Bronner, vice president of Rambus Labs. “Our strategic partnership with Microsoft has enabled us to identify new architectural models as we strive to develop systems utilizing cryogenic memory. The expansion of this collaboration will lead to new applications in high-performance supercomputers and quantum computers.”
Rambus Advances Smart Data Acceleration Research Program with LANL
November 29, 2015 by
Last week at SC15, Rambus announced that it has partnered with Los Alamos National Laboratory (LANL) for evaluating elements of its Smart Data Acceleration (SDA) Research Program. The SDA platform has been deployed at LANL to improve the performance of in-memory databases, graph analytics and other Big Data applications.
Rambus Collaborates with Intel on R+ DDR4 Server Memory
August 17, 2015 by
After a long absence, Rambus is back in the news with their announcement of the RB26 DDR4 server memory chipset. Developed in cooperation with Intel, the RB26 is an enhanced, JEDEC-compliant memory module chipset designed to accelerate data-intensive applications, including real-time analytics, virtualization and in-memory computing, with increased speed, reliability and power-efficiency.
