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Video: Applications Performance Optimizations – Best Practices


“To achieve good scalability performance on the HPC scientific applications typically involves good understanding of the workload through performing profile analysis, and comparing behaviors of using different hardware which pinpoint bottlenecks in different areas of the HPC cluster. In this session, a selection of HPC applications will be shown to demonstrate various methods of profiling and analysis to determine the bottleneck, and the effectiveness of the tuning to improve on the application performance.”

Managing a Hadoop Cluster

Hadoop Cluster

Hadoop configuration and management is very different than that of HPC clusters. Develop a method to easily deploy, start, stop, and manage a Hadoop cluster to avoid costly delays and configuration headaches. Hadoop clusters have more “moving software parts” than HPC clusters; any Hadoop installation should fit into an existing cluster provisioning and monitoring environment and not require administrators to build Hadoop systems from scratch. Learn about managing a Hadoop cluster from the insideHPC article series on Successful HPC Clusters.

Interview: Mellanox Announces World’s First 100Gb/s EDR InfiniBand Switch


In this video from ISC’14, Gilad Shainer from Mellanox provides a technology update. This week the company announced the World’s First 100Gb/s EDR InfiniBand Switch as well as the HPC-X Scalable Software Toolkit.

Mellanox Demonstrates World’s First 100Gb/s EDR InfiniBand Switch


Today Mellanox announced Switch-IB, the next generation of its InfiniBand switch and the first-ever switch IC capable of 100Gb/s per port speeds.

MVAPICH2 and MVAPICH2-X Projects: Latest Developments and Future Plans


“This talk will focus on latest developments and future plans for the MVAPICH2 and MVAPICH2-X projects. For the MVAPICH2 project, we will focus on scalable and highly-optimized designs for pt-to-pt communication (two-sided and one-sided MPI-3 RMA), collective communication (blocking and MPI-3 non-blocking), support for GPGPUs and Intel MIC, support for MPI-T interface and schemes for fault-tolerance/fault-resilience. For the MVAPICH2-X project, will focus on efficient support for hybrid MPI and PGAS (UPC and OpenSHMEM) programming model with unified runtime.”

Video: The SKA Project – The World’s Largest Streaming Data Processor

Paul Celleja

The Square Kilometre Array Design Studies are an international effort to investigate and develop technologies which will enable us to build an enormous radio astronomy telescope with a million square meters of collecting area.

Preparing for HPC Cloud Computing

HPC Cloud

Make sure you use Cloud services that are designed for HPC applications including high-bandwidth, low-latency networking, exclusive node use, and high performance compute/storage capabilities for your application set. Develop a very flexible and quick Cloud provisioning scheme that mirrors your local systems as much as possible, and is integrated with the existing workload manager. An ideal solution is where your existing cluster can be seamlessly extended into the Cloud and managed/monitored in the same way as local clusters. Read more from the insideHPC Guide to Managing HPC Clusters.

Looking Forward: The Intel Parallel Universe at ISC’14


Mike Bernhardt from Intel writes that the company will continue to demonstrate an “unswerving commitment to HPC” at next week’s International Supercomputing Conference. “If you want to keep up with where HPC is going, be sure to catch as many of the Intel presentations as you can fit into your calendar. They’ll be pretty hard to miss.”

Radio Free HPC Looks at PCIe 4.0 Delays and the New HP Apollo Servers


In this podcast, the Radio Free HPC team looks newly announced delays for the PCIe 4.0 specification and why this is bad news for high performance computing. After that, the topic switches to the new liquid-cooled Apollo 8000 servers from HP.

Fujitsu Labs Develops 56 Gbps CPU Communications Circuit


This week Fujitsu Laboratories announced a new receiver circuit capable of receiving communications at 56 Gbps, a world-record data rate between CPUs.