Leaders in hybrid accelerated HPC in the United States, Japan, and Switzerland have signed a memorandum of understanding establishing an international institute dedicated to common goals, the sharing of HPC expertise, and forward-thinking evaluation of computing architecture. “Forecasting the future of leadership-class computing and managing the risk of architectural change is a shared interest among ORNL, Tokyo Tech, and ETH Zurich,” said Jeff Nichols, associate laboratory director of computing and computational sciences at ORNL. “What unites our three organizations is a willingness to embrace change, actively partner with HPC vendors, and devise solutions that advance the work of our scientific users. ADAC provides a framework for member organizations to pursue mutual interests such as accelerated node architectures as computing moves toward the exascale era and beyond.”
“We are very excited to be working closely with Bright Computing to bring its supercomputing software tools to the embedded Aerospace & Defense market as part of our OpenHPEC Accelerator Suite software development toolset,” said Lynn Bamford, Senior Vice President and General Manager, Defense Solutions division. “Together, we are providing HPEC system integrators with proven and robust development tools from the Commercial HPC market to speed and ease the design of COTS-based highly scalable supercomputer-class solutions.”
Industry veterans Jason Coposky and Terrell Russell have taken lead roles at the membership-based foundation that leads development and support of the integrated Rule-Oriented Data System (iRODS). “With data becoming the currency of the knowledge economy, now is an exciting time to be involved with developing and sustaining a world-class data management platform like iRODS,” said Coposky. “Our consortium membership is growing, and our increasing ability to integrate with commonly used hardware and software is translating into new users and an even more robust product.”
Today Allinea Software launched the first update to its well-established toolset for debugging, profiling and optimizing high performance code since being acquired by ARM in December 2016. “The V7.0 release provides new integrations for the Allinea Forge debugger and profiler and Allinea Performance Reports and will mean more efficient code development and optimization for users, especially those wishing to take software performance to new levels across Xeon Phi, CUDA and IBM Power platforms,” said Mark O’Connor, ARM Director, Product Management HPC tools.
“U.S. Patent 9,496,200 protects the invention of utilizing a modular, building block approach for datacenter cooling with direct contact liquid cooling,” said Geoff Lyon CEO, CoolIT Systems. “CoolIT’s commitment to developing and patenting unique solutions provides our customers with the assured competitive advantage they are looking for. The 60 patent milestone adds confirmation to CoolIT’s leadership in developing innovative liquid cooling solutions for modern data centers.”
Today Silicon Valley startup Tachyum Inc. launched, announcing its mission to conquer the performance plateau in nanometer-class chips and the systems they power. “We have entered a post-Moore’s Law era where performance hit a plateau, cost reduction slowed dramatically, and process node shrinks and CPU release cycles are getting longer,” said Danilak, Tachyum CEO. “An innovative new approach, from first principles is the only realistic chance we have of achieving performance improvements to rival those that powered the tech industry of past decades, and the opportunity is a hundred times greater than any venture I’ve been involved in.”
Today the Active Archive Alliance announced that Oak Ridge National Laboratory (ORNL) has upgraded its active archive solutions to enhance the integrity and accessibility of its vast amount of data. The new solutions allow ORNL to meet its increasing data demands and enable fast file recall for its users. “These active archive upgrades were crucial to ensuring our users’ data is both accessible and fault-tolerant so they can continue performing high-priority research at our facilities,” said Jack Wells, director of science for the National Center for Computational Sciences at ORNL. “Our storage-intensive users have been very pleased with our new data storage capabilities.”
Kathy Yelick, the Associate Lab Director for Computing Sciences at LBNL, has been named to the Alameda County Women’s Hall of Fame for her leadership in science, technology and engineering. Twelve women, each representing a different field, were named as 2017 inductees. “According the organization’s announcement, Yelick is being recognized as “an international leader in computational sciences and a leading force in applying high performance computing to efforts to develop alternative energy sources and combat climate change. She is an advocate for diversity in computer science education and the use of computing to solve societal challenges.”
A technology-leading Fortune 100 company has deployed over 30,000 Supermicro MicroBlade servers, at its Silicon Valley data center facility with a Power Use Effectiveness (PUE) of 1.06, to support the company’s growing compute needs. Compared to a traditional data center running at 1.49 PUE, or more, the new datacenter achieves an 88percent improvement in overall energy efficiency. When the build out is complete at a 35 megawatt IT load power, the company is targeting $13.18M in savings per year in total energy costs across the entire datacenter.