Entries filed under “Green HPC”

Design and management techniques that contribute to the responsible, effective use of energy in the operation of high performance computing centers and equipment.

nCore HPC Rolls Out BrownDwarf ARM DSP Supercomputer

We don’t get the chance to announce new players in the HPC space very often, especially from our hometown of Portland. Today newcomers nCore HPC announced the BrownDwarf Y-class supercomputer, a heterogeneous ARM- and DSP-based system designed for green high performance computing.

With its unique parallel computing architecture and a high performance, low latency interconnect, the BrownDwarf is “Y-Class supercomputer” with extremely low power consumption. In a 144 node configuration, BrownDwarf delivers 70 Teraflops of performance at 10kw inside a 42U high rack.

The BrownDwarf Y-Class system is an incredibly important milestone in HPC system development,” said Ian Lintault, managing director of nCore HPC. “Working in close collaboration with TI, IDT and our hardware partner Prodrive, we have successfully established a new class of energy efficient supercomputers designed to fulfill the demands of a wide range of scientific, technical and commercial applications.”

The BrownDwarf Y-Class node leverages multiple Keystone-II and Keystone-I SoC components from Texas Instruments Incorporated (TI). Each node integrates four ARM Cortex-A15 MPCore processors, 24 TMS320C66x digital signal processor (DSP) cores and 26GB of ECC memory.

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Also posted in Accelerators, Compute, HPC, HPC Hardware | Leave a comment

E4 to Showcase Kayla GPU-ARM Development Platform at ISC’13

Nvidia made waves in March with the announcement of the Kayla development platform for CUDA on ARM processors. Next week at ISC’13 in Germany, E4 Computer Engineering will demonstrate its new, low-power E4 ARKA SERIES, a Kayla device equipped with an Nvidia Tegra Quad-Core ARM A9 CPU as well as an Nvidia GPU.

For the datacenter, E4 will also demonstrate the ARKA EK002, a 3U dual-node server featuring Nvidia Tegra3 CPU QUAD-Core ARM and a Kepler K20 GPUs configured with a Mellanox ConnectX-3 FDR 56Gb/s InfiniBand Adapter. The device is designed to be a development platform for HPC, Finance, and Energy applications.

To learn more, check out the E4 booth #267 at ISC’13.

Also posted in GPUs, HPC, HPC Hardware | Leave a comment

Pedraforca Cluster to be First to combine ARM CPUs, GPUs, and InfiniBand

Today the Barcelona Supercomputing Center (BSC) announced plans to deploy its next-gen ARM prototype cluster for HPC in July. Powered by ARM Cortex-A9, Nvidia Tesla K20 GPUs, and Mellanox QDR InfiniBand, the hybrid supercomputer will be named Pedraforca.

By using InfiniBand, Pedraforca enables direct GPU-to-GPU communication through RDMA on ARM. It features a low-power Nvidia Tegra® 3 (4-core Cortex-A9) to run the operating system and drive both the Tesla K20 accelerator and the QDR InfiniBand at the minimum power consumption.

Prototypes are critical to accelerate software development, both system software and applications. Pedraforca introduces multiple innovations to the ARM software stack, leading to a more energy-efficient platform for those GPU-centric applications that match the characteristics of the cluster.” says Alex Ramirez, leader of the Heterogeneous Architectures Research Group at BSC.

BSC deployed the first ARM-based multicore HPC cluster in October 2011 with a cluster called Tibidabo. In November 2012, BSC collaborated with NVIDIA and SECO in the development of the KAYLA development platform, the first hybrid ARM + CUDA GPU platform, which was field-tested in the second BSC cluster. Pedraforca represents another step forward in the BSC research roadmap on new technologies and innovative architectures towards energy-efficient HPC.

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Also posted in Computing Research, HPC, New Installations | Leave a comment

Video: Greener Buildings Through the HPC4Energy Incubator

In this video, Dr. J. Michael McQuade, Senior Vice President, Science and Technology at United Technologies, and Dr. Bob LaBarre, Principal Mathematician & Group Leader for System Dynamics & Optimization at United Technologies Research Center (UTRC), discuss the collaboration between UTRC and Lawrence Livermore National Laboratory with the HPC4Energy Incubator.

In order to best understand the impacts of a large number of building parameters, UTRC aims to run thousands of simulations, exploring the building model parameter space. By parallelizing these simulations, the time required to complete the thousands of simulations will be reduced from weeks to a few hours. The information provided by these simulations will allow building operators to understand which parameters play the most significant roles in building energy usage and how one might vary these parameters within acceptable comfort ranges to affect this usage. This information also will help building operators eager to retrofit their building to gain energy efficiency and reduce operation costs.

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Interview: Asetek to Demonstrate Direct-to-Chip Liquid Cooling at ISC’13

Asetek has been gaining traction with their liquid cooling technology for the datacenter. After checking out their impressive display at SC12, I decided to circle back with Asetek’s Steve Branton to learn more about what the company has in store for ISC’13 in Leipzig.

insideHPC: Asetek is known for its innovative cooling technologies for extreme PCs. What does your company have to offer the HPC marketplace?

Steve Branton: In the extreme PC market the benefit of our technology is performance, especially for over-clocking. We are also know for providing the same cooling technology for workstation PCs. In the workstation market the benefit is silent operation. Both of these benefits flow from the fact that our liquid cooling technology is more efficient than air cooling. More efficient cooling is the direct benefit we are bringing to the HPC market using the same proven technology. This technology allows HPC data centers to lower their cooling costs, increase density and even recycle the power used by their supercomputers for things like building and water heating.

insideHPC: It seems like more and more high end supercomputers are being deployed with some form of liquid cooling. Does this trend represent a growing business opportunity for Asetek?

Steve Branton: Absolutely.

insideHPC: Is liquid cooling only practical for the very high end of supercomputing?

Steve Branton: No. Asetek liquid cooling is practical for the whole of the HPC market. Certainly if one looks at very high-end supercomputers it is easy to conclude that liquid cooling is expensive. However, the cost of liquid cooling in these systems is more a result these computers being manufactured in rather small volumes which makes everything about them rather expensive. The use of centralized pumping and the associated high pressure design also contributes to the cost of these systems. Asetek uses a distributed pumping model, a low pressure pump on each CPU and GPU. The pumps are arranged in series, giving redundancy. With this approach Asetek is able to do is leverage our manufacturing scale from the desktop market to enable liquid cooling that is affordable across the whole spectrum of HPC product offerings. In particular, we expect to see adoption in the x86 segment of the HPC space.

insideHPC: You recently announced some wins in the U.S. federal space. What do you think are the key differentiators that helped you win the day?

Steve Branton: The US federal government operates close to 2,500 data centers today and many of them have been in operation for quite some time and many were designed at a time when energy efficiency was not a priority. The government has recognized that substantial cost savings opportunities exist. They have mandated both data center consolidation down to approximately 800 data centers and energy efficiency improvements. The government views both reductions in cooling energy and recycling of the energy used to run servers as energy efficiency gains. Asetek’s RackCDU products are capable of increasing density which enables consolidation into existing sites, lowers the energy need to cool data centers and enables the recycling of IT energy. Moreover it is capable of delivering these benefits with at a cost that often has a payback period of less than one year.

insideHPC: What will Asetek be showcasing in your booth at ISC’13?

Steve Branton: We will be showcasing our direct-to-chip (D2C) RackCDU hot-water liquid cooling systems which is available for deployment today. The Cray CS300-LC is the first supercomputer available with this cooling system. We will show case the Cray system as well as several prototypes show casing Asetek Direct to Chip liquid cooling implementations on servers from HP, Cisco and Fujitsu. By cooling the hot-spots in a server (CPUs, GPUs, and memory) these systems remove 60 to 80% of the heat generated by servers with facilities supply water that can be as hot as 40°C.

We will also be showing a prototype of our next generation In-Server Air Conditioning (ISAC) RackCDU system. ISAC is a warm water liquid cooling system that makes it possible to operate servers in hostile environments and in CRAC-less data centers.

insideHPC: What makes ISC’13 appealing to you as an HPC exhibitor?

Steve Branton: European energy markets make the financial benefits of Asetek RackCDU quite strong for data centers operating in the EU. The high server utilization rates common in HPC data centers shortens the time to reaching a positive ROI from liquid cooling. The European Union’s strong stance on environmental leadership provides a favorable social climate that encourages companies and data centers to innovate in energy efficiency. This combination of financial and political forces makes Europe a strong market for Asetek Liquid Cooling. ISC’13 is well positioned to reach the EU supercomputing community and to raise awareness within the community of what is possible with hot-water liquid cooling.

Also posted in Events, HPC, HPC Hardware, ISC13 | Leave a comment

Whitepaper: Creating a Raspberry Pi-Based Beowulf Cluster

The Raspberry Pi is a credit-card-sized single-board computer developed in the UK by the Raspberry Pi Foundation with the intention of promoting the teaching of basic computer science in schools. But could this ARM-based device be used to teach supercomputing as well? Joshua Kiepert, a doctoral student at Boise State’s Electrical and Computer Engineering department, published a white paper entitled: Creating a Raspberry Pi-Based Beowulf Cluster.

Although an inexpensive bill of materials looks great on paper, cheaper parts come with their own set ofdownsides. Perhaps the biggest downside is that an RPi is no where near as powerful as a current x86 PC. The RPi has a single-core ARM1176 (ARMv6) processor, running at 700MHz (though overclockingis supported). Additionally, since the RPi uses an ARM processor, it has a different architecture than PCs, i.e. ARM vs x86. Thus, any MPI program created originally on x86 must be recompiled when deployed to the RPiCluster. Fortunately, this issue is not present for java, python, or perl programs. Finally, because of the limited processing capability, the RPiCluster will not support multiple users simultaneously using the system very well. As such, it would be necessary to create some kind of timesharing system for access if it ever needed to be used in such a capacity.

Download the paper (PDF).

Also posted in Computing Research, HPC, Video | 1 Comment

Winston Saunders on Exascalar and Cost-effective HPC

Over the Intel Datastack Blog, Winston Saunders writes considering the rapidly expanding efficiency and performance capability of supercomputing systems, it may be time to upgrade just for the electricity savings alone.

You can see system-level annualized energy costs in the Figure. From this point it is pretty straight forward to calculate a payback time for replacing inefficient servers. It’s interesting they work out to be vertical lines. It’s interesting that they times for return on investment show up as vertical lines. It’s astounding that they are so short. In several cases, less than a year!

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Green Graph 500 Launches to Boost Energy Efficient Big Data Computing

In this special guest feature, Torsten Hoefler from ETH Zurich writes that the new Green Graph500 aims to boost energy-efficient Big Data Computing.

“Big Data” can be analyzed in various ways. The most successful and prevalent programming model, MapReduce, convinces by its flexibility toadapt to hardware performance variations and faults. However, even though MapReduce covers a huge majority of use-cases, it has its limits for graph computations. Complex graph algorithms become more important as our analysis capabilities grow. For example, problems such as finding hubs in social network graphs are routinely answered today. The underlying algorithm, betweenness centrality, utilizes a graph traversal similar to breadth first search or shortest path search. Systems such as Google’s Pregal, Apache’s Giraph, the (Parallel) Boost Graph Library, and Stanford’s GPS are just some examples for emerging frameworks to handle large-scale graph computations. In order to efficiently compare architectures and possibly programming frameworks, the Graph 500 benchmark strives to establish a database for performance of a standardized breadth first search on various platforms.

As energy is becoming a bigger concern than hardware purchasing costs in large-scale data centers and supercomputing centers, it becomes mandatory to not only consider the performance of such computations but also their exact energy consumption. In fact, if the current cost trends continue, then energy consumption will soon be more important than absolute performance. Such discussions are highly relevant for operators of large data centers such as Google, Amazon, and Yahoo, as well as large supercomputing centers operated by the DOE (e.g., LLNL, Sandia,LANL, ORNL) and the NSF (e.g., NCSA, SDSC, PSC). We are thus looking forward to interesting future developments targeting exascale as well as Big Data architectures and programming frameworks.

We introduce the Green Graph 500 list which fulfills a variety of purposes. First and foremost it is to establish the practice to compete not only for the highest performance but also for the highest energy efficiency, directly benefiting society. It is also set out to collect historical data about developments that may allow us to predict future trends very similar to what the top 500 list has achieved in the past(who doesn’t like to put up a top 500 slide to project out FLOP rate for the next 10 years?). The list will also allow us to compare the energy efficiency of a specific computer for certain tasks, e.g.,dense linear algebra (a problem mainly limited by memory size and CPU peak floating point performance) versus graph search (a problem mainly limited by memory access rates and global system bandwidth). Those two metrics together may serve as a measure to generate more efficient balanced systems as well as special-purpose systems for one of those tasks.

Finally, the new Green Graph 500 list is not meant to compete with any of the existing lists. It is indeed complementary, filling an important gap in the field. In fact, the rules are designed to be similar to the established Green 500 rules (similar, not identical, for example with regards to the network) so that comparisons can easily be made in the future. It also directly integrates with the Graph 500 list and submission system to guarantee one-to-one comparisons (a submission record may be in the Green Graph 500 as well as the Graph 500 even though the lists are ranked by different indices).

The Green Graph 500 list is soliciting submissions from everyone through the Graph 500 submission system. To submit to the list, simply start a normal Graph 500submission and select “Submit to Green Graph 500″ or “Submit to both lists”. The only additional data you need for a Green Graph 500submission is the actual power draw of your system during the benchmark.

Another small difference between Graph 500 and it’s Green peer is the measurement methodology. Since most power meters are not accurate enough to measure the rather short actual BFS run (not including the post-check etc.), we offer a slightly modified version of the reference benchmark which allows to run the BFS in a tight loop long enough for a low-time resolution energy meter to measure the exact energy consumption. This benchmark will also report a Graph 500 number valid for submission. For runs with a custom implementation, this would need to be ensured manually (4-5 lines of C Code suffice for this). The submission opens together with the official Graph 500 submission.

As a sneak peek, we prepared a sample list from March 2013′s energy submissions (which may not have followed all the official rules, thus, the list is not official).

The Green Graph 500 list is maintained by Torsten Hoefler from ETH Zurich in collaboration with the Graph 500 executive committee. For questions or comments please contact [email protected]

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Mont Blanc Targets Scientific Applications for Energy Efficient HPC

 

While many are looking at ARM-based processing as the future of energy-efficient HPC, it won’t get far without applications. Now, the Mont Blanc project has published a list of key scientific apps to be ported to the platform.

The Mont Blanc project aims to assess the potential of low-power embedded components based clusters to address future Exascale HPC needs. Among other objectives, we also aim to assess on the different generation of platforms made available by the project the behaviour of up to eleven real exascale-class scientific applications. These eleven real scientific applications, used by academia and industry, running daily in production into existing European (PRACE Tier-0 systems) or national HPC facilities have been selected by the different partners in order to cover a wide range of scientific domains (geophysics, fusion, materials, particle physics, life sciences, combustion, weather forecast) as well as hardware and software needs.

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IBM’s SuperMUC at LRZ to Reach 6.4 Petaflops

HPC System SuperMUC, installed at GCS centre Leibniz Supercomputing Centre (LRZ) in Garching near Munich, has commenced the second part of its installation with a performance upgrade.

Nine months after its inauguration, an agreement was sealed for a planned system expansion to be completed by end of 2014 or early 2015. The upgrade of the LRZ supercomputer, SuperMUC, which currently delivers a peak performance of 3.185 petaflops and holds position 6 on the Top500 list, will boost the system’s performance by a factor of about 2.1, making it capable of 6.4 petaflops.

The contract for SuperMUC Phase II was signed by representatives of all parties involved: Arndt Bode of the Leibniz Supercomputing Centre (LRZ), Karl-Heinz Hoffmann (chair of Bayerische Akademie der Wissenschaften), Martina Koederitz (general manager of IBM Germany), and Andreas Pflieger (IBM) in the presence of Wolfgang Heubisch and Georg Antretter representing the Bavarian State Ministry of Sciences, Research and the Arts.

The agreement states that 74,302 Intel-Xeon processor cores will be added to the existing 155,656 processor cores of SuperMUC. Its main memory will be expanded from 340 to 538 terabytes and 9 petabytes of intermediate storage will complement the system’s existing capacity of 10 petabytes.

The LRZ HPC system has been designed for exceptionally versatile deployment. The more than 150 different applications running on SuperMUC on average per year range from solving problems in physics and fluid dynamics to a wealth of other scientific fields, such as aerospace and automotive engineering, medicine and bioinformatics, astrophysics and geophysics amongst others.

Professor Bode is confident that SuperMUC Phase II will be running as stably and reliably as the current system has done from day one – and that it will scale to the large number of cores.

Only shortly after starting operation, SuperMUC was working to full capacity. Already, there are applications that practically use the entire system, and they do this in a very efficient way. Especially in the realm of biology and life sciences, we expect a significantly higher demand of system performance in the foreseeable future. SuperMUC Phase II will be in an excellent position to meet these requirements,’ said Bode.

This story appears here as part of a cross-publishing agreement with Scientific Computing World.

Also posted in Compute, HPC, HPC Hardware, New Installations | Leave a comment

Adaptiva Delivers Parallella Low-cost Parallel Chip Board for Linux Supercomputing

Say hi to Parallella, the $99 Linux-powered supercomputer. (Image: The Linux Foundation)

Over at ZDnet, Steven J. Vaughan-Nichols writes that chip-company Adapteva has built their first Parallella parallel-processing board for Linux supercomputing and will be sending them to their 6,300 Kickstarter supporters and other customers by this summer.

What Adapteva has done is create a credit-card sized parallel-processing board. This comes with a dual-core ARM A9 processor and a 64-core Epiphany Multicore Accelerator chip, along with 1GB of RAM, a microSD card, two USB 2.0 ports, 10/100/1000 Ethernet, and an HDMI connection. If all goes well, by itself, this board should deliver about 90 GFLOPS of performance, or — in terms PC users understand — about the same horse-power as a 45GHz CPU. This board will use Ubuntu Linux 12.04 for its operating system. To put all this to work, the platform reference design and drivers are now available.

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Video: Green Policies and Auto Power Management

In this video from Moabcon 2013, Gary Brown from Adaptive Computing presents: Green Policies and Auto Power Management.

This talk will help you understand Moab’s Power Management capabilities and how one might leverage the powerful capabilities of Moab’s Auto Power Management in one’s HPC environment to increase efficiency and reduce costs. Customer use cases will be presented to illustrate the ways leading companies are implementing these features to achieve real and significant results. Additionally, we will discuss best practices and general trends that we see in market today and in these best practices and trends influence Adaptive Computing’s product roadmap. Time will be allotted to accommodate a robust discussion around best practices and future product considerations.”

For more presentation videos, check out the Moabcon 2013 Video Gallery.

Also posted in Events, HPC, Moab.con, Video | Leave a comment

Biggest Names in Cloud are Turning to Liquid Cooling

Christopher Mims at Quartz reports that many of the big players in the Cloud space are migrating from air-controlled cooling to liquid cooling systems lead by companies like Green Revolution and Asetek.

In an un-air-conditioned shed in a location Price will not disclose, alongside bags of salt used to run a water softening system, sit waist-high tanks full of mineral oil. In their depths are tiny lights blinking like bioluminescent creatures from the abyss, and something even more unexpected: row after row of PC motherboards, craggy with RAM and CPUs and hard drives and cables. Each one is more or less straight off the rack—the same hardware that, in any other data center, would be cooled by an air-moving infrastructure that begins with gigantic air-conditioning systems and ends in palm-sized fans attached directly to the motherboards themselves.

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Jack Dongarra Visits Europe’s Largest Intel Xeon Phi Supercomputers from RSC Group

Tornado Supercomputer. (Pictured from left to right): Oleg Aladyshev (JSCC RAS), Jack Dongarra, Pavel Telegin (JSCC RAS) Alexey Ovsyannikov (JSCC RAS) Boris Shabanov (Deputy Director, JSCC RAS)

In a recent trip to Russia, renowned HPC expert Jack Dongarra visited two of Europe’s top Intel Xeon Phi supercomputer sites deployed by RSC Group, the Russian leading innovative HPC solutions builder. As the first Xeon Phi supercomputers outside of the USA being already ranked by Top500 and Green500, the systems are deployed at South Ural State University (SUSU) and Joint Supercomputer Center of Russian Academy of Science (JSCC RAS).

Both SUSU and JSCC RAS are state of the art high performance computing centers with competent staff running the highly ranked Top500 and Green500 powerful and energy efficient supercomputers,” said Jack Dongarra. “The facilities both use RSC Tornado based systems with innovative liquid cooling and newest Intel Xeon Phi coprocessors which provide impressive high performance capabilities and energy efficient solutions to solve very demanding science research and engineering problems.”

Dongarra was very impressed by high level of energy efficiency and world record computing (up to 181 TFLOPS per rack) and power (up to 100 kW per rack) density while having a very small footprint because of RSC Tornado liquid cooling technology implemented in the those both Russian projects.

This is a very simple and economical way to do it – in terms of the used space and power – which provides a good environment for the computer systems as well as for the people who take care of it. I see here a rather small room being equipped by a very powerful supercomputing system. I think this is a good sign of the well done engineering and planning have gone into construction of this computing facility.”

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NICS, Adaptive Computing, and Intel: Leadership in HPC

In this video from Moabcon 2013, Troy Baer presents: NICS, Adaptive Computing, and Intel: Leadership in HPC.

An Appro Xtreme-X Supercomputer named Beacon, deployed by the National Institute for Computational Sciences (NICS) of the University of Tennessee, tops the current Green500 list, which ranks the world’s fastest supercomputers based on their power efficiency. To earn its number-one ranking, the supercomputer employed Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors to produce 112.2 trillion calculations per second using only 44.89 kW of power, resulting in world-record efficiency of 2.499 billion floating point operations per second per watt.”

Read the Full Story or View the Slides on Slideshare. For more presentations, check out the Moabcon 2013 Video Gallery.

Also posted in Co-processors, Events, HPC, HPC Hardware, Moab.con, Video | Leave a comment

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