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Hewlett Packard Enterprise and Intel Alliance Delivers New Centers of Excellence for HPC

Intel and Hewlett Packard Enterprise (HPE) have recently created two new Centers of Excellence (CoE) to help customers gain hands-on experience with High Performance Computing (HPC). This plus collaboration with customers on implementing the latest technology solutions are highlights being celebrated by the two companies on the one-year anniversary of their alliance.

NSF Awards $110 Million for XSEDE 2.0

Today, the National Science Foundation (NSF) announced a $110 million award to the University of Illinois at Urbana-Champaign and 18 partner institutions to continue and expand activities undertaken through the Extreme Science and Engineering Discovery Environment (XSEDE).

Avere Systems Teams with Cycle Computing for High Performance Multi-cloud Orchestration

Today Avere Systems and Cycle Computing announced a technology integration that enables hybrid high-performance computing (HPC) in popular public cloud computing environments. By integrating the Avere vFXT Edge filer cloud bursting technology with Cycle Computing’s CycleCloud offering, users are now able to launch an Avere tiered file system on demand linked directly with the CycleCloud managed scalable compute nodes through cloud providers like AWS, Google Cloud Platform and Microsoft Azure.

Fujitsu Unveils Processor Details for Post-K Computer

The Fujitsu Journal has posted details on a recent Hot Chips presentation by Toshio Yoshida about the instruction set architecture (ISA) of the Post-K processor. “The Post-K processor employs the ARM ISA, developed by ARM Ltd., with enhancements for supercomputer use. Meanwhile, Fujitsu has been developing the microarchitecture of the processor. In Fujitsu’s presentation, we also explained that our development of mainframe processors and UNIX server SPARC processors will continue into the future. The reason that Fujitsu is able to continuously develop multiple processors is our shared microarchitecture approach to processor development.”

ARM Ramps up for HPC with SVE Scalable Vector Extensions

Over at the ARM Community Blog, Nigel Stephens writes that the company has introduced scalable vector extensions (SVE) their A64 instruction set to bolster high performance computing. Fujitsu is developing a new HPC processor conforming to ARMv8-A with SVE for the Post-K computer.

Tutorial: GPU Performance Nuggets

In this video from the 2016 Blue Waters Symposium, GPU Performance Nuggets – Carl Pearson and Simon Garcia De Gonzalo from the University of Illinois present: GPU Performance Nuggets. “In this talk, we introduce a pair of Nvidia performance tools available on Blue Waters. We discuss what the GPU memory hierarchy provides for your application. We then present a case study that explores if memory hierarchy optimization can go too far.”

Video: Combining Simulation & Experiment for Nanoscale 3-D Printing

In this video, ORNL researchers use supercomputers to simulate nanomanufacturing, the process of building microscopic devices atom by atom. Simulated here is the construction of a 250-nanometer 3-D cube by focused electron beam induced deposition.

OpenPOWER Summit Europe Comes to Barcelona Oct. 26-28

Today the OpenPOWER Foundation announced that their inaugural OpenPOWER Summit Europe will take place Oct. 26-28 in Barcelona, Spain. Held in conjunction with OpenStack Europe, the OpenPOWER Summit Europe, the event will feature speakers and demonstrations from the OpenPOWER ecosystem, including industry leaders and academia sharing their technical solutions and state of the art advancements.

Video: What is Driving Heterogeneity in HPC?

Wen-mei Hwu from the University of Illinois at Urbana-Champaign presented this talk at the Blue Waters Symposium. “In the 21st Century, we are able to understand, design, and create what we can compute. Computational models are allowing us to see even farther, going back and forth in time, learn better, test hypothesis that cannot be verified any other way, and create safe artificial processes.”

NERSC Dungeon Session Speeds Code for Cori Supercomputer

Six application development teams from NERSC gathered at Intel in early August for a marathon “dungeon session” designed to help tweak their codes for the next-generation Intel Xeon Phi Knight’s Landing manycore architecture and NERSC’s new Cori supercomputer. “We try to prepare ahead of time to bring the types of problems that can only be solved with the experts at Intel and Cray present—deep questions about the architecture and how applications use the Xeon Phi processor. It’s all geared toward optimizing the codes to run on the new manycore architecture and on Cori.”