Chandler, Ariz., February 2, 2021 – Microchip Technology Inc. (Nasdaq: MCHP) today announced what it said are the first PCI Express (PCIe) 5.0 switch solutions — the Switchtec PFX PCIe 5.0 family — “doubling the interconnect performance for dense compute, high speed networking and NVM Express (NVMe) storage,” according to the company. Together with the […]
GigaIO and Microchip Power Native PCI Express Network Fabric for Composable Disaggregated Infrastructure
January 14, 2021 by
Carlsbad, CA – January 17, 2021 – GigaIO, maker of data center network architecture and connectivity solutions, has announced a collaboration with Microchip Technology Inc. to power GigaIO’s FabreX, the native PCI Express (PCIe) Gen4 network fabric, which supports GDR, MPI, TCP/IP and NVMe-oF. FabreX technology revolutionizes rack-scale architectures, enabling software-defined, dynamically reconfigurable rack-scale systems, […]
Microchip Announces PCI Express 5.0 and CXLTM 2.0 Retimers
November 12, 2020 by
Chandler, AZ, November 10, 2020 – Microchip Technology Inc. announced today the XpressConnect family of low-latency PCI Express (PCIe®) 5.0 and Compute Express Link™ (CXLTM) 1.1/2.0 retimers. XpressConnect retimers triple the reach of PCIe Gen 5 electrical signals, which enables data center equipment providers to harness the next generational advancement in compute IO performance while […]
AI Workflow Scalability through Expansion
November 9, 2020 by
In this special guest feature, Tim Miller, Braden Cooper, Product Marketing Manager at One Stop Systems (OSS), suggests that for AI inferencing platforms, the data must be processed in real time to make the split-second decisions that are required to maximize effectiveness. Without compromising the size of the data set, the best way to scale the model training speed is to add modular data processing nodes.
Zero to an ExaFLOP in Under a Second
October 29, 2020 by
In this sponsored post, Matthew Ziegler at Lenovo discusses today’s metric for raw speed of compute. Much like racing cars, servers do “time trials” to gauge their performance relative to a given workload. There are more Spec or Web benchmarks out there for servers than there are racetracks and drag strips. Perhaps the most important measure is the raw calculating throughput that a system delivers: FLOPS, or Floating-Point Operations Per Second.
Choosing the Best Data Flow Design for GPU Accelerated Applications
October 28, 2020 by
In this sponsored article from our friends over at Supermicro, we discusses how deciding on the correct type of GPU accelerated computation hardware depends on many factors. One particularly important aspect is the data flow patterns across the PCIe bus and between GPUs and Intel® Xeon® Scalable processors. These factors, along with some application insights are explored below.
Practical Hardware Design Strategies for Modern HPC Workloads – Part 3
October 26, 2020 by
This special research report sponsored by Tyan discusses practical hardware design strategies for modern HPC workloads. As hardware continued to develop, technologies like multi-core, GPU, NVMe, and others have allowed new application areas to become possible. These application areas include accelerator assisted HPC, GPU based Deep learning, and Big Data Analytics systems. Unfortunately, implementing a general purpose balanced system solution is not possible for these applications. To achieve the best price-to-performance in each of these application verticals, attention to hardware features and design is most important.
Practical Hardware Design Strategies for Modern HPC Workloads – Part 2
October 21, 2020 by
This special research report sponsored by Tyan discusses practical hardware design strategies for modern HPC workloads. As hardware continued to develop, technologies like multi-core, GPU, NVMe, and others have allowed new application areas to become possible. These application areas include accelerator assisted HPC, GPU based Deep learning, and Big Data Analytics systems. Unfortunately, implementing a general purpose balanced system solution is not possible for these applications. To achieve the best price-to-performance in each of these application verticals, attention to hardware features and design is most important.
Practical Hardware Design Strategies for Modern HPC Workloads
October 16, 2020 by
This special research report sponsored by Tyan discusses practical hardware design strategies for modern HPC workloads. As hardware continued to develop, technologies like multi-core, GPU, NVMe, and others have allowed new application areas to become possible. These application areas include accelerator assisted HPC, GPU based Deep learning, and Big Data Analytics systems. Unfortunately, implementing a general purpose balanced system solution is not possible for these applications. To achieve the best price-to-performance in each of these application verticals, attention to hardware features and design is most important.
Practical Hardware Design Strategies for Modern HPC Workloads
October 12, 2020 by Leave a Comment
Many new technologies used in High Performance Computing (HPC) have allowed new application areas to become possible. Advances like multi-core, GPU, NVMe, and others have created application verticals that include accelerator assisted HPC, GPU based Deep Learning, Fast storage and parallel file systems, and Big Data Analytics systems. In this special insideHPC technology guide sponsored by our friends over at Tyan, we look at practical hardware design strategies for modern HPC workloads.
