“Building on the success of the Intel Parallel Computing Centers, Intel is announcing the Intel Modern Code Developer Community to help HPC developers to code for maximum performance on current and future hardware. Targeting over 400,000 HPC-focused developers and partners, the program brings tools, training, knowledge and support to developers worldwide by offering access to a network of elite experts in parallelism and HPC. The broader developer community can now gain the skills needed to unlock the full potential of Intel hardware and enable the next decade of discovery.”
In this video from the Intel booth at ISC 2015, Dr Juha Jäykkä, COSMOS System Manager at University of Cambridge describes a cosmology demonstration running on prototype Intel Knights Landing and Omni-Path hardware. “At ISC 2015, unveiled new details for its future generation high performance computing products, including the first public “powered-on” demonstration of the Intel Omni-Path Architecture, a next-generation fabric technology optimized for HPC deployments.”
“HPC has reached an inflection point with the convergence of traditional high performance computing and the emerging world of Big Data analytics. Intel’s HPC Scalable System Framework enables an unprecedented level of system balance, performance, and scalability necessary to meet the demands of bot compute- and data-intensive workloads, today and well into the future.”
The benefits of nested parallelism on highly threaded applications can be determined and quantified. With the number of cores in both the host CPU (Intel Xeon) and the coprocessor (Intel Xeon Phi) continues to increase, much thought must be given to minimizing the thread overhead when many threads need to be synchronized, as well as the memory access for each processor (core). Tasks that can be spread across an entire system to exploit the algorithm’s parallelism, should be mapped to the NUMA node to make them more efficient.
In this video from ISC 2015, Intel’s Raj Hazra explores how new innovations and Intel’s Scalable System Framework approach can maximize the potential in the new HPC era. Raj also shares details of upcoming Intel technologies, products and ecosystem collaborations that are powering these breakthroughs and ensuring technical computing continues to fulfill its potential as a scientific and industrial tool for discovery and innovation.
“Applications can be tuned to use both the Intel Xeon and the Intel Xeon Phi simultaneously, without modifying the code to just run on the coprocessor. Using a number of software tools from Intel, performance of a coupled cluster method can be demonstrated to gain a tremendous performance with excellent scaling.”
Dr. Eng Lim Goh from SGI discusses important trends in HPC including pending changes coming to processors/accelerators, memory hierarchy, and interconnects. “SGI, the trusted leader in high performance computing, is focused on helping customers solve their most demanding business and technology challenges by delivering technical computing, Big Data analytics, cloud computing, and petascale storage solutions that accelerate time to discovery, innovation, and profitability.”
Today Nallatech announced the 510T FPGA co-processor. Designed to deliver ultimate performance per watt for compute-intensive datacenter applications, the 510T is a GPU-sized 16-lane PCIe 3.0 card featuring two of Altera’s new floating-point enabled Arria 10 FPGAs delivering up to sixteen times the performance of the previous generation. According to Nallatech, applications can achieve a total sustained performance of up to 3 TFlops.
Designating the appropriate provider for large MPI applications is critical to taking advantage of all of the compute power available. “A modern HPC system with multiple host cpus and multiple coprocessors such as the Intel Xeon Phi coprocessor housed in numerous racks can be optimized for maximum application performance with intelligent thread placement.”