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Nallatech Rolls Out 510T FPGA Accelerator

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Today Nallatech announced the 510T FPGA co-processor. Designed to deliver ultimate performance per watt for compute-intensive datacenter applications, the 510T is a GPU-sized 16-lane PCIe 3.0 card featuring two of Altera’s new floating-point enabled Arria 10 FPGAs delivering up to sixteen times the performance of the previous generation. According to Nallatech, applications can achieve a total sustained performance of up to 3 TFlops.

Computing With MPI in Heterogeneous Environments

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Designating the appropriate provider for large MPI applications is critical to taking advantage of all of the compute power available. “A modern HPC system with multiple host cpus and multiple coprocessors such as the Intel Xeon Phi coprocessor housed in numerous racks can be optimized for maximum application performance with intelligent thread placement.”

Concurrent Kernel Offloading

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“The combination of using a host cpu such as an Intel Xeon combined with a dedicated coprocessor such as the Intel Xeon Phi coprocessor has been shown in many cases to improve the performance of an application by significant amounts. When the datasets are large enough, it makes sense to offload as much of the workload as possible. But is this the case when the potential offload data sets are not as large?”

Why Hardware is Leaving Software Behind

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In the first report from last week’s PRACEdays15 conference in Dublin, Tom Wilkie from Scientific Computing World considers why so much Exascale software will be open source and why engineers are not using parallel programs.

Load Balancing Using OpenMP 4.0

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OpenMP 4.0 standard now allows for the offloading of portions of the application, in order to take more advantage of many-core accelerators such as the Intel Xeon Phi coprocessor.

New Whitepaper: Multi-Threading and Parallel Reduction for Xeon Phi

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Colfax Research has published a new whitepaper entitled: Multi-Threading and Parallel Reduction. As part 1 of a 3-part educational series, the paper authored by Ryo Asai and Andrey Vladimirov focuses on optimization of applications for the Intel Xeon processors and Intel Xeon Phi coprocessors.

Direct N-Body Simulation

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In some domains, an N-Body simulation is key to solving for the movement and forces of a dynamic system of particles. At each time step, the force that one body exacts on each other, and then the velocity can be computed. The simulation can continue up to a desired number of time steps.

Advanced Clustering Builds 32 Teraflop “Buddy” Supercomputer

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Today Advanced Clustering Technologies announced that the University of Central Oklahoma’s Center for Research and Education in Interdisciplinary Computation (CREIC) has selected the company to build their next supercomputer. The 32 Teraflop HPC cluster will be named “Buddy” in honor of the university’s mascot, Buddy Bronco.

Thinkmate Offers Free Xeon Phis with Your Server

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We don’t normally report on pricing, but a free Intel Xeon Phi from ThinkMate sure sounds like a great deal. “Now through June, Thinkmate is installing Intel Xeon Phi 5110P Coprocessors (a $2,500 value each) for Free with any compatible server.”

HPC News Bytes for May 15, 2015

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While we’re always on the lookout for HPC news, not everything makes it to the front page. Here are some notable items from this week.