April 14, 2022 – Today, the OCP Foundation, the nonprofit organization focused on hyperscale, announced a new hardware-software co-design strategy that is exemplified by recent contributions to the OCP by Microsoft and Intel of the Scalable I/O (Input/Output) Virtualization (SIOV) specification, and a new collaboration with the SONiC Project now at the Linux Foundation. “Hardware–software co-design […]
Co-Design 3.0 – Configurable Extreme Computing, Leveraging Moore’s Law for Real Applications
January 2, 2017 by
Sadasivan Shankar gave this Invited Talk at SC16. “This talk will explore six different trends all of which are associated with some form of scaling and how they could enable an exciting world in which we co-design a platform dependent on the applications. I will make the case that this form of “personalization of computation” is achievable and is necessary for applications of today and tomorrow.”
Exascale Computing Project Gains Momentum Entering Year 2
November 21, 2016 by
In this video from SC16, Paul Messina and Stephen Lee describe the mission, status, and recent milestones of the Exascale Computing Project. Now entering its second year, the ECP recently announced that it has selected four co-design centers as part of a 4 year, $48 million funding award. It also announced the selection of 35 software development proposals representing 25 research and academic organizations.
The insideHPC Guide to Co Design Architecture
August 31, 2016 by Leave a Comment
The use of Co-Design and offloading are important tools in achieving Exascale computing. Application developers and system designers can take advantage of network offload and emerging co-design protocols to accelerate their current applications. Adopting some basic co-design and offloading methods to smaller scale systems can achieve more performance on less hardware resulting in low cost and higher throughput. Learn more by downloading this guide.
Video: Nvidia’s Peter Messmer on Co-Design at PASC16
July 13, 2016 by
In this video from PASC16, Peter Messmer from Nvidia gives his perspectives on the conference and his work on co-design for high performance computing. “Using a combination of specialized rather than one type fits all processing elements offers the advantage of providing the most economical hardware for each task in a complex application. In order to produce optimal codes for such heterogeneous systems, application developers will need to design algorithms with the architectural options in mind.”
Interview: Why Co-design is the Path Forward for Exascale Computing
March 4, 2016 by
“Co-Design is a collaborative effort among industry thought leaders, academia, and manufacturers to reach Exascale performance by taking a holistic system-level approach to fundamental performance improvements. Co-Design architecture enables all active system devices to become acceleration devices by orchestrating a more effective mapping of communication between devices in the system. This produces a well-balanced architecture across the various compute elements, networking, and data storage infrastructures that exploits system efficiency and even reduces power consumption.”
UCX: Co-Design Architecture For Next Generation HPC Systems
September 28, 2015 by
“The UCX Unified Communication X project is a collaboration between industry, laboratories, and academia to create an open-source production grade communication framework for data centric and high-performance applications. At the core of the UCX project are the combined features, ideas, and concepts of industry leading technologies including MXM, PAMI and UCCS. Mellanox Technologies has contributed their MXM technology, which provides enhancements to parallel communication.”
Advancing HPC with Collaboration & Co-design
August 2, 2015 by
In this special guest feature from Scientific Computing World, Tom Wilkie reports on two US initiatives for future supercomputers, announced at the ISC in Frankfurt in July.
How CoDesign Helps Shape Successful Hardware and Software Development
January 8, 2015 by
“In working to improve future hardware and software for its simulation requirements, Sandia National Laboratories are engaging in co-design efforts with major hardware vendors. In this talk recent improvements influenced by the collaboration with NVIDIA will be discussed. The presentation will in particular focus on newly available experimental C++11 support in CUDA and how this facilitates both more rapid porting of applications to GPUs as well as better exploitation of GPU architecture characteristics. Furthermore, initial performance studies on NVIDIA’s next generation Tesla product line will be presented as well as first impressions of an IBM POWER-8 based GPU cluster.”
