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Video: Moore’s Law is Not Dead

Jim Keller from Intel gave this talk at the EECS Colloquium. “While it is true that certain vectors like transistor performance and power are showing diminishing returns, other vectors like transistor architecture, microprocessor architecture, software and new materials are showing increasing returns. The combination of these will continue to make life interesting and challenging for hardware and software designers alike.”

John Shalf from LBNL on Computing Challenges Beyond Moore’s Law

In this special guest feature from Scientific Computing World, Robert Roe interviews John Shalf from LBNL on the development of digital computing in the post Moore’s law era. “In his keynote speech at the ISC conference in Frankfurt, Shalf described the lab-wide project at Berkeley and the DOE’s efforts to overcome these challenges through the development acceleration of the design of new computing technologies.”

Video: The Challenge of Heterogeneous Compute & Memory Systems

Mike Ignatowski from AMD gave this talk at the Rice Oil & Gas conference. “We have reached the point where further improvements in CMOS technology and CPU architecture are producing diminishing benefits at increasing costs. Fortunately, there is a great deal of room for improvement with specialized processing, including GPUs and other emerging accelerators. In addition, there are exciting new developments in memory technology and architecture coming down the development pipeline.”

European LEGaTO Project aims to Develop Software for Energy Efficient Computing

A new European project aims to overcome the energy efficiency challenges of heterogeneous computing architectures by developing a new software stack. “Moore´s Law is slowing down, and as consequence hardware is becoming more heterogeneous. In the LEGaTO project, we will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. Our aim is one order of magnitude energy savings from the edge to the converged cloud/high-performance computing.”

PASC17 to Feature Panel Discussions on Moore’s Law and Computational Sciences

The upcoming PASC17 conference has posted further details on a pair of panel discussions taking place at the conference next month. The conference takes place June 26-28 in Lugano, Switzerland.

Dr. William Vanderlinde on Computing Beyond Moore’s Law

In this video from the IEEE Rebooting Computing Workshop, Dr. William Vanderlinde, Chief Scientist at Intelligence Advanced Research Projects Activity (IARPA), explains how we have already entered the era at the end of Moore’s law, including the end of Dennard Scaling. Dr. Vanderlinde also reviews the National Strategic Computing Initiative (NSCI) and IARPA’s focus in relation to the NSCI’s objectives.

Call for Papers: Workshop on HPC in a post Moore’s Law World

“The impending end of traditional MOSFET scaling has sparked research into preserving HPC performance improvements through alternative computational models. To better shape our strategy, we need to understand where each technology is headed and where it will be in a span of 20 years. This workshop brings together experts who develop or use promising technologies to present the state of their work, and spark a discussion on the promise and detriments of each approach.”

Co-Design 3.0 – Configurable Extreme Computing, Leveraging Moore’s Law for Real Applications

Sadasivan Shankar gave this Invited Talk at SC16. “This talk will explore six different trends all of which are associated with some form of scaling and how they could enable an exciting world in which we co-design a platform dependent on the applications. I will make the case that this form of “personalization of computation” is achievable and is necessary for applications of today and tomorrow.”

Satoshi Matsuoka Presents: The Inevitable End of Moore’s Law

“The promising new parameter in place of the transistor count is the perceived increase in the capacity and bandwidth of storage, driven by device, architectural, as well as packaging innovations: DRAM-alternative Non-Volatile Memory (NVM) devices, 3-D memory and logic stacking evolving from VIAs to direct silicone stacking, as well as next-generation terabit optics and networks. The overall effect of this is that, the trend to increase the computational intensity as advocated today will no longer result in performance increase, but rather, exploiting the memory and bandwidth capacities will instead be the right methodology.”

PRACEdays15 Puts the Spotlight on Irish HPC

In this report from PRACEdays15 conference in Dublin last week, Robert Roe from Scientific Computing World looks at the role of HPC in the host country, Ireland.