A new supercomputer has been deployed at the Jülich Supercomputing Center (JSC) in Germany. Called QPACE3, the new 447 Teraflop machine is named for “QCD Parallel Computing on the Cell. “QPACE3 is being used by the University of Regensburg for a joint research project with the University of Wuppertal and the Jülich Supercomputing Center for numerical simulations of quantum chromodynamics (QCD), which is one of the fundamental theories of elementary particle physics. Such simulations serve, among other things, to understand the state of the universe shortly after the Big Bang, for which a very high computing power is required.”
Podcast: Intel Doubles Down on Artificial Intelligence
December 23, 2016 by
In this Chip Chat podcast, Diane Bryant, EVP/GM for the Data Center Group at Intel, discusses how the company is driving the future of artificial intelligence by delivering breakthrough performance from best-in-class silicon, democratizing access to technology, and fostering beneficial uses of AI. Bryant also outlines her vision for AI’s ability to fundamentally transform the way businesses operate and people engage with the world. In a blog Krzanich said: “Intel is uniquely capable of enabling and accelerating the promise of AI. Intel is committed to AI and is making major investments in technology and developer resources to advance AI for business and society.”
Speed Your Application with Threading Building Blocks
December 22, 2016 by
With modern processors that contain a large number of cores, to get maximum performance it is necessary to structure an application to use as many cores as possible. Explicitly developing a program to do this can take a significant amount of effort. It is important to understand the science and algorithms behind the application, and then use whatever programming techniques that are available. “Intel Threaded Building Blocks (TBB) can help tremendously in the effort to achieve very high performance for the application.”
Supermicro Showcases Versatile HPC Solutions at SC16
December 9, 2016 by
In this video from SC16, Don Clegg from Supermicro describes the company’s broad range of HPC solutions. “Innovation is at the core of Supermicro product development and benefits the HPC community with first-to-market integration of advanced technology such as our 1U with four and 4U with eight Pascal P100 SXM2 GPUs or 4U with ten PCI-e GPU systems, hot-swap U.2 NVMe, upcoming fabric technologies like Red Rock Canyon and PCI-E switches, as well as new architecture designs like our new high-density BigTwin system design.”
Optimizing Your Code for Big Data
December 8, 2016 by
Libraries that are tuned to the underlying hardware architecture can increase performance tremendously. Higher level libraries such at the Intel Data Analytics Acceleration Library (Intel DAAL) can assist the developer with highly tuned algorithms for data analysis as well as machine learning. Intel DAAL functions can be called within other, more comprehensive frameworks that deal with the various types of data and storage, increasing the performance and lowering the development time of a wide range of applications.
Kx Streaming Analytics Crunches 1.2 Billion NYC Taxi Data Points using Intel Xeon Phi
December 5, 2016 by
“The complexity and high costs of architecting and maintaining streaming analytics solutions often make it difficult to get new projects off the ground. That’s part of the reason Kx, a leading provider of high-volume, high-performance databases and real-time analytics solutions, is always interested in exploring how new technologies may help it push streaming analytics performance and efficiency boundaries. The Intel Xeon Phi processor is a case in point. At SC16 in Salt Lake City, Kx used a 1.2 billion record database of New York City taxi cab ride data to demonstrate what the Intel Xeon Phi processor could mean to distributed big data processing. And the potential cost/performance implications were quite promising.”
Lenovo Boosts Marconi Supercomputer to 6.2 Petaflops with Intel Xeon Phi
December 4, 2016 by
“Phase one at CINECA, an academic consortium, was completed in May 2016 – coming in at 1.7 Petaflops, which at the time it was the largest Intel Omni-Path Fabric system in the world. Lenovo and CINECA are pleased to announce the delivery and installation of phase two, a 3,600 node Intel Xeon Phi processor which is interconnected with 100Gb Intel Omni-Path fabric – delivering 6.2 Petaflops of performance.”
Intel Xeon Phi with Software Defined Visualization at SC16
December 2, 2016 by
“Software Defined Visualization (SDVis) is an open source initiative from Intel and industry collaborators to improve the visual fidelity, performance and efficiency of prominent visualization solutions – with a particular emphasis on supporting the rapidly growing “Big Data” usage on workstations through HPC supercomputing clusters without the memory limitations and cost of GPU based solutions. Existing applications can be enhanced using the high performing parallel software rendering libraries OpenSWR, Embree, and OSPRay. At the Intel HPC Developer Conference, Amstutz provided an introduction to this initiative, its benefits, a brief descriptions of accomplishments in the past year and talk about the changes made to Intel provided libraries in the past year.”
Best Threads Per Core with Intel Xeon Phi
December 1, 2016 by
“When designing an application that contains many threads and less cores than threads, it is important to understand what is the optimal number of threads that should be assigned to a core. This value should be parameterized, in order to easily run tests to determine which is the optimum value for a given machine. One thread per core on the Intel Xeon Phi processor will give the highest performance per thread. When the number of threads per core is set at two or four, the individual thread performance may be lower, but the aggregate performance will be greater.”
Asetek Lands Nine Installations on the Green500
November 30, 2016 by
“As seen at installations included on both the Green500 and Top500 lists, Asetek’s distributed liquid cooling architecture enables cluster energy efficiency in addition to sustained and un-throttled cluster performance,” said John Hamill, Vice President of WW Sales and Marketing. “Around the world, data centers are increasingly using Asetek technology for High Performance Computing while reducing energy costs.”
