To get maximum performance from the Intel Xeon Phi, applications may have to be re-thought to take advantage of the SIMD architecture.
At the Centre for High-Performance Computing (CHPC) in South Africa, the mission is to enable cutting-edge research by supporting the highest levels of HPC available. That means ensuring researchers – who often are not experienced with computers let alone HPC systems – to get their work done with the HPC getting in the way.
“As the use of coprocessors increases to speedup HPC applications, it is important to understand how much additional power the coprocessors use. With various measurements and benchmarks arising to calculate the power used during the running of compute and data intensive applications, measuring the power draw from an Intel Xeon Phi coprocessor is important to understanding the best use of resources.”
Designating the appropriate provider for large MPI applications is critical to taking advantage of all of the compute power available. “A modern HPC system with multiple host cpus and multiple coprocessors such as the Intel Xeon Phi coprocessor housed in numerous racks can be optimized for maximum application performance with intelligent thread placement.”
“The combination of using a host cpu such as an Intel Xeon combined with a dedicated coprocessor such as the Intel Xeon Phi coprocessor has been shown in many cases to improve the performance of an application by significant amounts. When the datasets are large enough, it makes sense to offload as much of the workload as possible. But is this the case when the potential offload data sets are not as large?”