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Slidecast: SSRLabs Develops Energy- and Instruction-Efficient HPC

SSRLabs_InsideHPC_August2013

Scalable Systems Research Labs is developing coprocessors to solve the “Big Data” problem by accelerating execution of applications.

Video: Interconnect for Tightly Coupled Accelerators Architecture

TCA

The Tightly Coupled Accelerators (TCA) architecture is designed to reduce the communication latency between accelerators over different nodes.

Video: Designing Optimized MPI Broadcast and Allreduce for MIC Architecture

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In this video from the 2013 Hot Interconnects Conference, Krishna Kandalla presents: Designing Optimized MPI Broadcast and Allreduce for Many Integrated Core (MIC) InfiniBand Clusters. The emergence of co-processors such as Intel Many Integrated Cores (MICs) is changing the landscape of supercomputing. The MIC is a memory constrained environment and its processors also operate at […]

Video: Compilation for Intel Xeon Phi

Intel Xeon Phi Webinar

In this video, Intel’s Martyn Corden presents: Compilation for Intel Xeon Phi. “This two day webinar series introduces you to the world of multicore and manycore computing with Intel Xeon processors and Intel Xeon Phi coprocessors. Expert technical teams at Intel discuss development tools, programming models, vectorization, and execution models that will get your development […]

Jim Jeffers on High Performance Programming for the Intel Xeon Phi Coprocessor

In this video from ISC’13, Jim Jeffers from Intel discusses the new Intel Xeon Phi product family and how programmers can take advantage of parallelism to optimize applications performance. Jeffers is the co-author of the book, Intel Xeon Phi Coprocessor High Performance Programming. Authors Jim Jeffers and James Reinders spent two years helping educate customers […]

Video: New Updates to Intel Xeon Phi

In this video from ISC’13, Stephen Chenoweth from Intel describes the latest additions to the Intel Xeon Phi coprocessor family. You can watch Intel’s product announcement right here on insideHPC and check out more from the show at our ISC’13 Video Gallery.

Video: Space Weather Simulation on Intel Xeon Phi

In this video from ISC’13, Hans-Christian Hoppe from Intel describes a space weather simulation powered by Intel Xeon Phi coprocessors.

Video: Driving Industrial Innovation on the Road to Exascale

In this video from ISC’13, Raj Hazra from Intel presents: Driving Industrial Innovation on the Road to Exascale. Join Intel for a look at the state of the HPC industry from two perspectives. First, we’ll look at how innovations in HPC are driving innovation in manufacturing industries with energy and automotive industry leaders providing examples. […]

Excitement at ISC13: Getting to the MilkyWay 2

In this special guest feature, Intel’s John Hengeveld describes the effort that went into building the fastest supercomputer on Earth. Milky Way 2 is amazing.. and whats more amazing is… you can build a similar system for your needs. So by now you have all heard about the MilkyWay 2 system in China that has […]

Tutorial on Scaling to Petaflops with Intel Xeon Phi

Over at Dr. Dobbs, Rob Farber has posted a tutorial on using MPI to tie together thousands of Intel Xeon Phi coprocessors. Farber uses his MPI code example on the Stampede supercomputer at TACC, achieving a remarkable 2.2 Petaflops of performance when running on 3000 nodes. This article demonstrates how to utilize Intel Xeon Phi […]