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Building Bridges to the Future

“The Pittsburgh Supercomputing Center recently added Bridges to its lineup of world-class supercomputers. Bridges is designed for uniquely flexible, interoperating capabilities to empower research communities that previously have not used HPC and enable new data-driven insights. It also provides exceptional performance to traditional HPC users. It converges the best of High Performance Computing (HPC), High Performance Data Analytics (HPDA), machine learning, visualization, Web services, and community gateways in a single architecture.”

See What’s New from Intel at ISC 2016

New HPC products and technologies. Compelling demos. Insights from top Intel HPC architects. More than 60 presentations from Intel and industry experts. Additional details about Intel® Scalable System Framework. Intel will have something for everyone at this year’s International Supercomputing Conference in Frankfurt, Germany.

Call for Presentations: MVAPICH User Group (MUG) Meeting

The MVAPICH User Group (MUG) meeting has issued its Call for Presentations. The event takes place August 15-17 in Columbus, Ohio.

Stampede 2 Supercomputer at TACC to Sport 18 Petaflops

Over at the Dell HPC Community, Jim Ganthier writes that TACC is planning to deploy its 18 Petflop Stampede 2 supercomputer based on Dell servers running Intel Knights Landing processors. “Stampede 2 will do more than just meet growing demand from those who run data-intensive research. Imagine the discoveries that will be made as a result of this award and the new system. Now more than ever is an exciting time to be in HPC.”

Data Layout for High Performance

For maximum performance, data needs to flow into and out of the vectorization units. There are a few things to remember regarding laying out the data to gain high performance. These include, data layout, alignment, prefetching, and store operations. “Prefetching is also extremely important in HPC applications that use coprocessors. If the vectors are aligned, then the data can be streamed to the math units very efficiently, with data being prefetched, rather than the system having to load registers from various memory storage.”

Agenda Posted for Exacom 2016 – Communication Architectures at Extreme Scale

The International Workshop on Communication Architectures at Extreme Scale has published its Advance Agenda. Now in its second year, Exacom 2016 will be held in conjunction with ISC 2016 in Frankfurt on Thursday, June 23, 2016.

Univa Grid Engine Adds Support for Docker Containers & Knights Landing

Today Univa announced the general availably of its Grid Engine 8.4.0 product. Enterprises can now automatically dispatch and run jobs in Docker containers, from a user specified Docker image, on a Univa Grid Engine cluster. This significant update simplifies running complex applications in a Grid Engine cluster and reduces configuration and OS issues. Grid Engine 8.4.0 isolates user applications into their own container, avoiding conflict with other jobs on the system and enables legacy applications in Docker containers and non-container applications to run in the same cluster.

Disruptive Opportunities and a Path to Exascale: A Conversation with HPC Visionary Alan Gara of Intel

“We want to encourage and support that collaborative behavior in whatever way we can, because there are a multitude of problems in government agencies and commercial entities that seem to have high performance computing solutions. Think of bringing together the tremendous computational expertise you find from the DOE labs with the problems that someone like the National Institutes of Health is trying to solve. You couple those two together and you really can create something amazing that will affect all our lives. We want to broaden their exposure to the possibilities of HPC and help that along. It’s important, and it will allow all of us in HPC to more broadly impact the world with the large systems as well as the more moderate-scale systems.”

Using Vectors on Intel Xeon Phi

The use of vector instructions can speed up applications tremendously when used correctly. The benefit is that much more work can be done in a clock cycle than by performing the operation one at a time. The Intel Xeon Phi coprocessor was designed with strong support for vector level parallelism. “When these techniques are used either individually or in combination in different areas of the application, the performance will surely be increased, in many cases without a lot of effort.”

Ryft: Bringing High Performance Analytics to Every Enterprise

Pat McGarry from Ryft presented this talk at the HPC User Forum in Tucson. “Years in the making, the Ryft ONE combines two proven innovations in hardware and software to optimize compute, storage and I/O performance: the Ryft Hybrid FPGA/x86 Compute Platform, which leverages a massively parallel bitwise computing architecture and the Ryft Algorithmic Primitives (RAP) Library.