In this video from the 2015 OFS Developer’s Workshop, Katie Antypas from LBNL describes preparations for the Cori supercomputer. “We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware threads. That a significant increase from both our Hopper and Edison system, which has 24 cores each.”
“This talk includes an overview of the present and future of the Intel Many Integrated Core architecture. I will illustrate the value proposition of Intel Xeon Phi coprocessors for scientific applications with case studies done at Colfax. Original training program will be featured, designed to help developers to get started with the MIC architecture.”
The University of Cambridge plans to transition their HPC workloads to Intel’s Xeon Phi co-processors. The deal will see Intel work along with Dell staff to upgrade the high performance infrastructure used to serve research departments within the university, working in areas such as genomics and astronomy, as well as a growing number of businesses with large compute demands.
The University of Houston (UH) is adding a new, state-of-the-art supercomputer to its arsenal of research tools. With 1860 compute cores, the new Opuntia cluster will be used primarily for scientific and engineering work. The acquisition of this new system marks the start of a new era of supercomputing not only for the University of […]
The Barcelona Supercomputing Center and Intel have renewed their collaboration research agreement at the Intel and BSC Exascale Laboratory in Barcelona. Now funded through 2017, the Intel and BSC Exascale Lab in Barcelona focuses on software and extraordinary levels of parallelism that will be needed to use future Intel-architecture-based supercomputers.