In this special guest feature, John Kirkley writes that Argonne is already building code for their future Theta and Aurora supercomputers based on Intel Knights Landing. “One of the ALCF’s primary tasks is to help prepare key applications for two advanced supercomputers. One is the 8.5-petaflops Theta system based on the upcoming Intel® Xeon Phi™ processor, code-named Knights Landing (KNL) and due for deployment this year. The other is a larger 180-petaflops Aurora supercomputer scheduled for 2018 using Intel Xeon Phi processors, code-named Knights Hill. A key goal is to solidify libraries and other essential elements, such as compilers and debuggers that support the systems’ current and future production applications.”
In this HPC Podcast, Don Kinhorn and Chris Stevens from Puget Systems discuss the boom in FPGAs at SC15 as well as Intel’s announcement that the company is going to maintain a build of Python. “Python is a pretty important programming language. It has a large and growing number of useful libraries for mathematical/scientific computing and machine learning, NumPy, SciPy, pandas, Scikit-learn, PySpark, theano, and more.”
In this special guest feature from Scientific Computing World, Andrew Jones from NAG looks ahead at what 2016 has in store for HPC and finds people, not technology, to be the most important issue. “A disconcertingly large proportion of the software used in computational science and engineering today was written for friendlier and less complex technology. An explosion of attention is needed to drag software into a state where it can effectively deliver science using future HPC platforms.”
In this video from SC15, NERSC shares its experience on optimizing applications to run on the new Intel Xeon Phi processors (code name Knights Landing) that will empower the Cori supercomputer by the summer of 2016. “A key goal of the Cori Phase 1 system is to support the increasingly data-intensive computing needs of NERSC users. Toward this end, Phase 1 of Cori will feature more than 1,400 Intel Haswell compute nodes, each with 128 gigabytes of memory per node. The system will provide about the same sustained application performance as NERSC’s Hopper system, which will be retired later this year. The Cori interconnect will have a dragonfly topology based on the Aries interconnect, identical to NERSC’s Edison system.”
“Aurora’s revolutionary architecture features Intel’s HPC scalable system framework and 2nd generation Intel Omni-Path Fabric. The system will have a combined total of over 8 Petabytes of on package high bandwidth memory and persistent memory, connected and communicating via a high-performance system fabric to achieve landmark throughput. The nodes will be linked to a dedicated burst buffer and a high-performance parallel storage solution. A second system, named Theta, will be delivered in 2016. Theta will be based on Intel’s second-generation Xeon Phi processor and will serve as an early production system for the ALCF.”
“The Intel’s next generation Xeon Phi processor family x200 product (code-name Knights Landing) brings in new memory technology, a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in addition to the traditional DDR4. MCDRAM is a high bandwidth (~4x more than DDR4), low capacity (up to 16GB) memory, packaged with the Knights Landing Silicon. MCDRAM can be configured as a third level cache (memory side cache) or as a distinct NUMA node (allocatable memory) or somewhere in between. With the different memory modes by which the system can be booted, it becomes very challenging from a software perspective to understand the best mode suitable for an application.”
“In this presentation, we will discuss several important goals and requirements of portable standards in the context of OpenMP. We will also encourage audience participation as we discuss and formulate the current state-of-the-art in this area and our hopes and goals for the future. We will start by describing the current and next generation architectures at NERSC and OLCF and explain how the differences require different general programming paradigms to facilitate high-performance implementations.”
Today Atos launched the Bull sequana X1000, its new family of supercomputers on the company’s road to exascale. “The new Bull sequana system, powered by future Intel Xeon processors and the Intel Xeon Phi processor, code-named “Knights Landing”, is designed to address the performance, reliability and energy-efficiency requirements of exascale-class supercomputers,” said Raj Hazra, vice president and general manager, Enterprise and HPC Platforms Group, Intel Corporation. “We’re excited to be collaborating with Bull to bring to market this new generation of supercomputers on the path to exascale.”
Today CoolIT Systems announced plans to showcase new server cooling technologies at the SC15 conference in Austin. Exhibiting at booth #163, CoolIT Systems will exhibit an expanded line of heat exchange solutions. Attendees will also find new customer case studies outlining the real-world benefits the industry is experiencing with liquid cooling.
The HPC industry’s expanded use of liquid cooling was evident at the recent ISC 2015 conference in Frankfurt. To learn more, we caught up with Steve Branton from Asetek.