While there have been previous generations of AVX instructions, the AVX-512 instructions can significantly assist the performance of HPC applications. “The new AVX-512 instructions have been designed with developers in mind. High level languages that are used for HPC applications, such as FORTRAN and C/C++, through a compiler will be able to use the new instructions. This can be accomplished through the use of pragmas to direct the compilers to generate the new instructions, or users can use libraries which are tuned to the new technology.”
“With up to 72 out-of-order cores, the new Intel Xeon Phi processor delivers over 3 teraFLOPS (floating-point operations per second) of double-precision peak while providing 3.5 times higher performance per watt than the previous generation. As a bootable CPU with integrated architecture, the Intel Xeon Phi processor eliminates PCIe* bottlenecks, includes on-package high-bandwidth memory, and available integrated Intel Omni-Path fabric architecture to deliver fast, low-latency performance.”
Adrian Jackson from EPCC at the University of Edinburgh presented this tutorial to ARCHER users. “We have been working for a number of years on porting computational simulation applications to the KNC, with varying successes. We were keen to test this new processor with its promise of 3x serial performance compared to the KNC and 5x memory bandwidth over normal processors (using the high-bandwidth, MCDRAM, memory attached to the chip).”
LANL reports that a moment of inspiration during a wiring diagram review has saved more than $2 million in material and labor costs for the Trinity supercomputer at Los Alamos National Laboratory.
Kyoto University Thinks Widening SIMD Will be Key to Performance Gains in New Intel Xeon Phi processor-based Cray System
“With an imminent switchover to a new Cray system with next-generation Intel Xeon Phi Processors (codenamed Knights Landing) planned for October, the ACCMS team at Kyoto University is eagerly looking forward to a potential two-fold application performance improvements from its new system. But the lab is also well aware that there is significant recoding work ahead before the promise of the new manycore technology can be realized.”
“Intel provided a wealth of machine learning announcements following the Intel Xeon Phi processor (formerly known as Knights Landing) announcement at ISC’16. Building upon the various technologies in Intel Scalable System Framework, the machine learning community can expect up to 38% better scaling over GPU-accelerated machine learning and an up to 50x speedup when using 128 Intel Xeon Phi nodes compared to a single Intel Xeon Phi node. The company also announced an up to 30x improvement in inference performance (also known as scoring or prediction) on the Intel Xeon E5 product family due to an optimized Intel Caffe plus Intel Math Kernel Library (Intel® MKL) package.”
Today Univa announced the general availably of its Grid Engine 8.4.0 product. Enterprises can now automatically dispatch and run jobs in Docker containers, from a user specified Docker image, on a Univa Grid Engine cluster. This significant update simplifies running complex applications in a Grid Engine cluster and reduces configuration and OS issues. Grid Engine 8.4.0 isolates user applications into their own container, avoiding conflict with other jobs on the system and enables legacy applications in Docker containers and non-container applications to run in the same cluster.
In this podcast, the Radio Free HPC team looks at the news highlights for the week leading up to Friday the 13th of May, 2016. Highlights include a 25 Petaflop Fujitsu supercomputer coming to Japan, an OpenPOWER Summit coming to Europe, and fighting the Zombie Apocalypse with HPC.
Today Fujitsu announced an order for a 25 Petaflop supercomputer system from the University of Tokyo and the University of Tsukuba. Powered by Intel Knights Landing processors, the “T2K Open Supercomputer” will be deployed at the Joint Center for Advanced High-Performance Computing (JCAHPC), which the two universities jointly operate. “The new supercomputer will be an x86 cluster system consisting of 8,208 of the latest FUJITSU Server PRIMERGY x86 servers running next-generation Intel Xeon Phi processors. Due to be completely operational in December 2016, the system is expected to be Japan’s highest-performance supercomputer.”
In this special guest feature, John Kirkley writes that Argonne is already building code for their future Theta and Aurora supercomputers based on Intel Knights Landing. “One of the ALCF’s primary tasks is to help prepare key applications for two advanced supercomputers. One is the 8.5-petaflops Theta system based on the upcoming Intel® Xeon Phi™ processor, code-named Knights Landing (KNL) and due for deployment this year. The other is a larger 180-petaflops Aurora supercomputer scheduled for 2018 using Intel Xeon Phi processors, code-named Knights Hill. A key goal is to solidify libraries and other essential elements, such as compilers and debuggers that support the systems’ current and future production applications.”