I’m on my way home from a series of Springtime HPC conferences with boatload of new videos and interviews on the latest in high performance computing. Here are some notable items that may have not made it to the front page.
“Confronting power limitations and the high cost of data movement, new supercomputing architectures within the DOE are requiring users make changes to application codes to achieve high performance. More specifically, users will need to exploit greater on-node parallelism and longer vector units, and restructure code to take advantage of memory locality. In this presentation you will learn about coming architectural trends and what you can do now to start preparing your application.”
“We are excited about launching NESAP in partnership with Cray and Intel to help transition our broad user base to energy-efficient architectures,” said Sudip Dosanjh, director of NERSC, the primary HPC facility for the DOE’s Office of Science. “We expect to see many aspects of Cori in an exascale computer, including dramatically more concurrency and on-package memory. The response from our users has been overwhelming—they recognize that Cori will allow them to do science that can’t be done on today’s supercomputers.”
In the course of this talk, Intel’s Raj Hazra unveils details of the Knights Landing architecture including the new Omni Scale Fabric, an integrated, high performance interconnect designed for CPU to CPU communications. “The industry ecosystem needs to work together to tackle challenges in system architecture, programming models, and energy efficiency – all while lowering the thresholds for broader user access and usability.”