Today Gidel announced the availability of new development tools that take advantage of Intel’s HLS, producing a speed increase of 5x over prior development options. Intel’s High Level Synthesis (HLS) compiler turns untimed C++ into Register Transfer Level (RTL) — a low- level FPGA code. Gidel’s development tools map board resources to application needs, and provide the glue between the host computer and the FPGA logic by building an Application Support Package (ASP). Gidel’s tools provide access for software developers to be able to work with HLS, and simplify integration of new IP that may utilize HLS into existing designs.
Mellanox Announces Innova-2 FPGA-Based Programmable Adapters
November 6, 2017 by
Today Mellanox announced the Innova-2 product family of FPGA-based smart network adapters. Innova-2 is the industry leading programmable adapter designed for a wide range of applications, including security, cloud, Big Data, deep learning, NFV and high performance computing. “Xilinx is pleased that our All Programmable UltraScale FPGAs are accelerating Mellanox’s Innova network adaptors,” said Manish Muthal, vice president of Data Center Business at Xilinx. “Our combined technology enables the rapid deployment of customized acceleration for emerging data center and high performance computing workloads.”
Intel awards Paderborn University a Hybrid Cluster with Arria 10 FPGAs
September 22, 2017 by
The Paderborn Center for Parallel Computing (PC²) has been selected by Intel to host a computer cluster that uses Intel’s Xeon processor with its Arria 10 FPGA software development platform.” The availability of these systems allows us to further expand our leadership in this area and – as a next step – bring Intel FPGA accelerators from the lab to HPC production systems,” says Prof. Dr. Christian Plessl, director of the Paderborn Center for Parallel Computing, who is been active in this research area for almost two decades.”
Moving to Exascale – Closer Than We Think?
March 10, 2017 by
“Back in 2013 I wrote the following blog expressing my opinion that I doubted we would reach Exascale before 2020. However, recently it was announced that the world’s first Exascale supercomputer prototype will be ready by the end of 2017 (recently pushed back to early 2018), created by the Chinese. I did some digging and wanted to share my thoughts on the news.”
FPGAs Accelerate Machine Learning at Baidu
October 30, 2016 by
Xilinx has announced that Baidu, a Chinese language Internet search provider, is utilizing Xilinx FPGAs to accelerate machine learning applications in its datacenters in China. “Acceleration is essential to keep up with the rapidly increasing data centre workloads that support our growth,” said Yang Liu, executive director at Baidu.
OpenPOWER Summit Europe Comes to Barcelona Oct. 26-28
August 21, 2016 by
Today the OpenPOWER Foundation announced that their inaugural OpenPOWER Summit Europe will take place Oct. 26-28 in Barcelona, Spain. Held in conjunction with OpenStack Europe, the OpenPOWER Summit Europe, the event will feature speakers and demonstrations from the OpenPOWER ecosystem, including industry leaders and academia sharing their technical solutions and state of the art advancements.
Ryft: Bringing High Performance Analytics to Every Enterprise
May 18, 2016 by
Pat McGarry from Ryft presented this talk at the HPC User Forum in Tucson. “Years in the making, the Ryft ONE combines two proven innovations in hardware and software to optimize compute, storage and I/O performance: the Ryft Hybrid FPGA/x86 Compute Platform, which leverages a massively parallel bitwise computing architecture and the Ryft Algorithmic Primitives (RAP) Library.
Using Xeon + FPGA for Accelerating HPC Workloads
March 26, 2016 by
“The Exascale computing challenge is the current Holy Grail for high performance computing. It envisages building HPC systems capable of 10^18 floating point operations under a power input in the range of 20-40 MW. To achieve this feat, several barriers need to be overcome. These barriers or “walls” are not completely independent of each other, but present a lens through which HPC system design can be viewed as a whole, and its composing sub-systems optimized to overcome the persistent bottlenecks.”
Anton 2 Supercomputer to Speed Molecular Simulations at PSC
February 4, 2016 by
Today the Pittsburgh Supercomputing Center (PSC) announced a $1.8-million National Institutes of Health grant to make the next-generation Anton 2 supercomputer developed by D. E. Shaw Research (DESRES) available to the biomedical research community. A specialized system for modeling the function and dynamics of biomolecules, the Anton 2 machine at PSC will be the only one of its kind publicly available to U.S. scientists. The grant also extends the operation of the Anton 1 supercomputer currently at PSC until the new Anton 2 is deployed, expected in the Fall of 2016.
