Today InAccel annnounced that it has integrated JupyterHub into the company’s adaptive acceleration platform for FPGAs. InAccel provides an FPGA resource manager that allows the instant deployment, scaling and virtualization of FPGAs making easier than ever the utilization of FPGA clusters for applications like machine learning, data processing, data analytics and many more HPC workloads.
Xilinx Alveo Accelerators Power Real-Time AI-based Intrusion Detection Service
November 5, 2019 by
Today Xilinx announced that SK Telecom has adopted Xilinx Alveo Datacenter Accelerator cards to power a real-time AI-based physical intrusion and theft detection service. SK Telecom’s AI inference accelerator (AIX) implemented on Xilinx Alveo cards provides efficient and accurate physical intrusion detection using deep neural networks. “In the era of Artificial Intelligence where new services are being deployed at unprecedented rates, we keep pursuing to innovate our cloud systems to deliver more value to our customers with more reliable and efficient services across diverse segments.”
Cortical.io Demonstrates Natural Language Understanding Inspired by Neuroscience
October 17, 2019 by
In this video, Cortical.io CEO Francisco Webber demonstrates how the company’s software running on Xilinx FPGAs breaks new ground in the field of natural language understanding (NLU). “Cortical.io delivers AI-based Natural Language Understanding solutions which are quicker and easier to implement and more capable than current approaches. The company’s patented approach enables enterprises to more effectively search, extract, annotate and analyze key information from any kind of unstructured text.”
Vitis Unified Software Platform to make FPGA Programming Accessible for All Developers
October 1, 2019 by
Since their beginnings, FPGA’s have been notorious for being hard to program. That could be changing with the new Vitis Unified Software Platform from Xilinx.n“Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimize both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon.”
High Speed Data Capture for AI on the Fly Edge Applications
August 8, 2019 by
In many AI applications, transporting large amounts of data back to a remote datacenter is impractical and undesirable. With AI on the Fly, the entire AI workflow resides at the edge at the data source. One Stop Systems’s Tim Miller explores how high performance scalable data acquisition is a fundamental and enabling component of this emerging new paradigm.
Xilinx Launches Alveo U50 FPGA Datacenter Accelerator Card
August 6, 2019 by
Today Xilinx launched the new Alveo U50 data center accelerator card, the industry’s first low profile adaptable accelerator with PCIe Gen 4 support. Designed for the datacenter, the Alveo U50 is uniquely designed to supercharge a broad range of critical compute, network and storage workloads, all on one reconfigurable platform. “We believe the combination of low-profile form-factor, HBM2 memory performance, and PCIe Gen 4 speed to interface with IBM Power processors will enable the OpenPOWER ecosystem to provide cutting edge adaptable acceleration solutions.”
HPE Speeds Gen10 Servers with Intel FPGA Programmable Acceleration Card D5005
August 5, 2019 by
HPE is now shipping HPE ProLiant DL380 Gen10 servers with the new Intel FPGA Programmable Acceleration Card D5005, the latest in a growing line of field programmable gate array-based, server-accelerator cards from Intel. “Compared to the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA, the Intel FPGA PAC D5005 accelerator card offers significantly more resources including three times the amount of programmable logic, as much as 32 GB of DDR4 memory (a 4x increase) and faster Ethernet ports (two 100GE ports versus one 40GE port).”
John Shalf from LBNL on Computing Challenges Beyond Moore’s Law
July 12, 2019 by
In this special guest feature from Scientific Computing World, Robert Roe interviews John Shalf from LBNL on the development of digital computing in the post Moore’s law era. “In his keynote speech at the ISC conference in Frankfurt, Shalf described the lab-wide project at Berkeley and the DOE’s efforts to overcome these challenges through the development acceleration of the design of new computing technologies.”
FPGAs and the Road to Reprogrammable HPC
July 3, 2019 by
In this special guest feature from Scientific Computing World, Robert Roe writes that FPGAs provide an early insight into possibile architectural specialization options for HPC and machine learning. “Architectural specialization is one option to continue to improve performance beyond the limits imposed by the slow down in Moore’s Law. Using application-specific hardware to accelerate an application or part of one, allows the use of hardware that can be much more efficient, both in terms of power usage and performance.”
Video: Can FPGAs compete with GPUs?
May 15, 2019 by
John Romein from ASTRON gave this talk at the GPU Technology Conference. “We’ll discuss how FPGAs are changing as a result of new technology such as the Open CL high-level programming language, hard floating-point units, and tight integration with CPU cores. Traditionally energy-efficient FPGAs were considered notoriously difficult to program and unsuitable for complex HPC applications. We’ll compare the latest FPGAs to GPUs, examining the architecture, programming models, programming effort, performance, and energy efficiency by considering some real applications.”
