Sign up for our newsletter and get the latest HPC news and analysis.
Send me information from insideHPC:


Offering Bare-Metal Performance and Scalability on Cloud: The Azure-HPC Approach

Jithin Jose from Microsoft gave this talk at the MVAPICH User Group. “This talk focuses on how HPC offerings in Azure address these challenges and explains the design pillars that allow Microsoft to offer “bare-metal performance and scalability” on the Microsoft Azure Cloud. This talk also covers the features of latest Microsoft Azure HPC offerings and provides in-depth performance insights and recommendations for using MVAPICH2 and MVAPICH2-X on Microsoft Azure.”

HPE Powers Research at DiRAC HPC Facility

“At HPE, we’ve seen many organizations struggle with technology that couldn’t handle enormous volumes of data. As a national facility serving a large research community, DiRAC needed HPC solutions that could manage complex workloads without the risk of downtime. It also needed more computing power, better storage capabilities, and faster processing to allow its researchers to compete internationally.”

Video: Managing HPC Software Complexity with Spack

Greg Becker from LLNL gave this talk at the MVAPICH User Group. “Spack is an open-source package manager for HPC. This presentation will give an overview of Spack, including recent developments and a number of items on the near-term roadmap. We will focus on Spack features relevant to the MVAPICH community; these include Spack’s virtual package abstraction, which is used for API-compatible libraries including MPI implementations, package level compiler wrappers, and packages which modify other package’s build environments.”

Intel Ships First 10nm Agilex FPGAs with Integrated Arm Processors

Today Intel announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. In what may be a surprise to many, the F-Series variant of the chip family also provides the option to integrate a quad-core Arm Cortex-A53 processor to provide high system integration. “Intel FPGAs have provided Microsoft tremendous value for accelerating real-time AI, networking, and other applications/infrastructure across Azure Cloud Services, Bing, and other data center services.”

Video: Mellanox Rolls Out SmartNICs

In this video, Mellanox CTO Michael Kagan talks about the next step for SmartNICs and the company’s newly released ConnectX-6 Dx product driven by its own silicon. “The BlueField-2 IPU integrates all the advanced capabilities of ConnectX-6 Dx with an array of powerful Arm processor cores, high performance memory interfaces, and flexible processing capabilities in a single System-on-Chip (SoC), supporting both Ethernet and InfiniBand connectivity up to 200Gb/s.”

The Confluence of HPC and AI – Intel Customer Use Cases

Vikram Saletore from Intel gave this talk at the MVAPICH User Group. “Intel collaborates with customers and partners worldwide to build, accelerate, scale and deploy their AI applications on Intel based HPC platforms. We share with you our insights on several customer AI use cases we have enabled, the orders of magnitude performance acceleration we have delivered via popular open-source software framework optimizations, and the best-known methods to advance the convergence of AI and HPC on Intel Xeon Scalable Processor based servers. We will also demonstrate how large memory systems help real world AI applications efficiently.”

Appentra Releases Parallelware Trainer 1.3

Appentra has released Parallelware Trainer 1.3, an interactive, real-time code editor with features that facilitate the learning, usage, and implementation of parallel programming by understanding how and why sections of code can be parallelized. “We’re happy to announce the release of Parallelware Trainer 1.3 which now supports the detection of defects and recommendations for concurrency and parallelism. We expect this new feature to further improve the learning process by providing feedback about code issues right in the integrated editor.”

Chapel Comes of Age: a Language for Productivity, Parallelism, and Performance

Brad Chamberlain from Cray gave this talk at the HPCKP’19 conference. “Though Chapel has been under development for some time now, its performance and feature  set have only recently reached the point where it can seriously be considered by users with HPC-scale scientific, data analytic, and artificial intelligence workloads. In this talk, I will introduce Chapel for those who are new to the language, and cover recent advances, milestones, and performance results for those who are already familiar with it.”

A Performance Comparison of Different MPI Implementations on an ARM HPC System

Nicholas Brown from EPCC gave this talk at the MVAPICH User Group. “In this talk I will describe work we have done in exploring the performance properties of MVAPICH, OpenMPI and MPT on one of these systems, Fulhame, which is an HPE Apollo 70-based system with 64 nodes of Cavium ThunderX2 ARM processors and Mellanox InfiniBand interconnect. In order to take advantage of these systems most effectively, it is very important to understand the performance that different MPI implementations can provide and any further opportunities to optimize these.”

Overview of the MVAPICH Project and Future Roadmap

DK Panda gave this talk at the MVAPICH User Group. “This talk will provide an overview of the MVAPICH project (past, present, and future). Future roadmap and features for upcoming releases of the MVAPICH2 software family (including MVAPICH2-X and MVAPICH2-GDR) for HPC and Deep Learning will be presented. Features and releases for Microsoft Azure and Amazon AWS will also be presented. Current status and future plans for OSU INAM, OMB, and Best Practices Page will also be presented.”